Scheduling and placement of hardware/software real-time relocatable tasks in dynamically partially reconfigurable systems

ACM Transactions on Reconfigurable Technology and Systems

Volumn 4, Issue 1, 2010, Pages

  Hsiung, Pao Ann ^a   Huang, Chun Hsian ^a   Shen, Jih Sheng ^a   Chiang, Chen Chi ^a  

^a NATIONAL CHUNG CHENG UNIVERSITY   (Taiwan)

Author keywords

Dynamically partially reconfigurable systems; Hardware resource utilization; Placement; Relocatable hardware software tasks; Scheduling

Indexed keywords

BEST EFFORT; DYNAMICALLY RECONFIGURABLE NETWORK; HARDWARE AND SOFTWARE; HARDWARE RESOURCE UTILIZATION; HARDWARE/SOFTWARE; MEMORY USAGE; PLACEMENT; PLACEMENT METHODS; QUADRATIC TIME; REAL TIME CONSTRAINTS; RECONFIGURABLE LOGIC; RECONFIGURABLE SYSTEMS; RELOCATABLE HARDWARE-SOFTWARE TASKS; RUNTIMES; TIME COMPLEXITY;

COMPUTER HARDWARE; RECONFIGURABLE HARDWARE; SCHEDULING;

HARDWARE;

EID: 84867497727     PISSN: 19367406     EISSN: 19367414     Source Type: Journal    
DOI: 10.1145/1857927.1857936     Document Type: Conference Paper

References (30)

1. ABENI, L. AND BUTTAZZO, G. 1998. Integrating multimedia applications in hard real-time systems. In Proceedings of the 19th IEEE Real-Time Systems Symposium. IEEE Computer Society, 4-13.
2. AHMADINIA, A. AND TEICH, J. 2003. Speeding up online placement for Xilinx FPGAs by reducing configuration overhead. In Proceedings of the IFIP International Conference on VLSI-SoC. 118-122.
3. AHMADINIA, A., BOBDA, C., BEDNARA, M., AND TEICH, J. 2004. A new approach for on-line placement on reconfigurable devices. In Proceedings of the International Parallel and Distributed Processing Symposium. IEEE CS Press, 134.
4. AHMADINIA, A., BOBDA, C., FEKETE, S. P., TEICH, J., AND VAN DER VEEN, J. C. 2004. Optimal routing-conscious dynamic placement for reconfigurable devices. In Proceedings of the 14th International Conference on Field-Programmable Logic and Applications. Lecture Notes in Computer Science, vol. 3203. Springer, 847-851.
5. AHMADINIA, A., BOBDA, C., AND TEICH, J. 2005. Online placement for dynamically reconfigurable devices. Int. J. Embed. Syst. 1, 3-4, 165-178.
6. ANDREWS, D., SASS, R., ANDERSON, E., AGRON, J., PECK, W., STEVENS, J., BAIJOT, F., AND KOMP, E. 2008. Achieving programming model abstractions for reconfigurable computing. IEEE Trans. VLSI Syst. 16, 4, 34-44.
7. BANERJEE, S., BOZORGZADEH, E., AND DUTT, N. D. 2006. Integrating physical constraints in hw-sw partitioning for architectures with partial dynamic reconfiguration. IEEE Trans. VLSI Syst. 14, 11.
8. BAZARGAN, K., KASTNER, R., AND SARRAFZADEH, M. 2000. Fast template placement for reconfigurable computing systems. IEEE Des. Test Comput. 17, 1, 68-83.
9. CHEN, Y.-H. AND HSIUNG, P.-A. 2005. Hardware task scheduling and placement in operating systems for dynamically reconfigurable SoC. In Proceedings of the 2005 IFIP International Conference on Embedded and Ubiquitous Computing (EUC'05). Lecture Notes in Computer Science, vol. 3824. Springer Verlag, 489-498.
10. CORBETTA, S., FERRANDI, F., MORANDI, M., SANTAMBROGIO, M., AND SCIUTO, D. 2007. Two novel approaches to online partial bitstream relocation in a dynamically reconfigurable system. In Proceedings of the Annual Symposium on VLSI. IEEE Computer Society Press.
11. DANNE, K. AND PLATZNER, M. 2005. Periodic real-time scheduling for FPGA computers. In Proceedings of the 3rd International Workshop on Intelligent Solutions in Embedded Systems (WISES'05). IEEE Computer Society, 117-127.
12. ELFARAG, A. A., EL-BOGHDADI, H. M., AND SHAHEEN, S. I. 2007. Miss ratio improvement for real-time applications using fragmentation-aware placement. In Proceedings of the IEEE International Parallel and Distributed Processing Symposium.
13. HANDA, M. AND VEMURI, R. 2004. An efficient algorithm for finding empty space for online FPGA placement. In Proceedings of the 41st Design Automation Conference (DAC'04). ACM Press, 960-965.
14. HORTA, E. AND LOCKWOOD, J. W. 2001. Parbit: A tool to transform bitfiles to implement partial reconfiguration of field programmable gate arrays (FPGAs). Tech. rep.WUCS-01-13,Washington University.
15. HSIUNG, P.-A. AND LIU, C.-W. 2007. Exploiting hardware and software low power techniques for energy efficient co-scheduling in dynamically reconfigurable systems. In Proceedings of the 17th International Conference on Field Programmable Logic and Applications (FPL'07). IEEE Computer Society Press, 165-170.
16. HUANG, C.-H., CHANG, S.-S., AND HSIUNG, P.-A. 2007. Generic wrapper design for dynamic swappable hardware IP in partially reconfigurable systems. Int. J. Elect. Engin. 14, 3, 229-238.
17. HUANG, C.-H. AND HSIUNG, P.-A. 2008. Software-controlled dynamically swappable hardware design in partially reconfigurable systems. EURASIP J. Embed. Syst. 231940.
18. KOCH, D., HAUBELT, C., STREICHERT, T., AND TEICH, J. 2007. Modeling and sythesis of hardware-software morphing. In Proceedings of the IEEE International Symposium on Circuits and Systems. 2746-2749.
19. LIAO, H.-W. 2007. Multi-objective placement of reconfigurable hardware tasks in real-time systems. M.S. thesis, National Chung Cheng University, Chiayi, Taiwan.
20. LOO, S. M. AND WELLS, B. E. 2005. Task scheduling in a finite-resource, reconfigurable hardware/ software codesign environment. INFORMS J. Comput. 18, 2, 151-172.
21. MEI, B., SCHAUMONT, P., AND VERNALDE, S. 2000. A hardware-software partitioning and scheduling algorithm for dynamically reconfigurable embedded systems. In Proceedings of the 11th ProRISC Workshop on Circuits, Systems and Signal Processing.
22. MORANDI, M., NOVATI, M., SANTAMBROGIO, M., AND SCIUTO, D. 2008. Core allocation and relocation management for a self dynamically reconfigurable architecture. In Proceedings of the Annual Symposium on VLSI. IEEE Computer Society Press, 286-291.
23. PECK, W., ANDERSON, E., AGRON, J., STEVENS, J., BAIJOT, F., AND ANDREWS, D. 2006. Hthreads: A computational model for reconfigurable devices. In Proceedings of the International Conference on Field Programmable Logic and Applications. 885-888.
24. PELLIZZONI, R. AND CACCAMO, M. 2006. Adaptive allocation of software and hardware realtime tasks for FPGA-based embedded systems. In Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06). IEEE Computer Society Press, 208-220.
25. PORRMANN, M., KALTE, H. G. L., AND RÜCKERT, U. 2005. Replica: A bitstream manipulation filter for module relocation in partial reconfigurable systems. In Proceedings of the 12th Reconfigurable Architectures Workshop.
26. STEIGER, C., WALDER, H., PLATZNER, M., AND THIELE, L. 2003. Online scheduling and placement of real-time tasks to partially reconfigurable devices. In Proceedings of the 24th IEEE International Real-Time Systems Symposium. IEEE Computer Society Press.
27. STEIGER, C., WALDER, H., AND PLATZNER, M. 2004. Operating systems for reconfigurable embedded platforms: Online scheduling of real-time tasks. IEEE Trans. Comput. 53, 11, 1393-1407.
28. TABERO, J., SEPTIEN, J., MECHA, H., AND MOZOS, D. 2004. A low fragmentation heuristic for task placement in 2D RTR HW management. In Proceedings of the International Conference on Field-Programmable Logic and Applications. Springer Verlag, 241-250.
29. WALDER, H. AND PLATZNER, M. 2003. Online scheduling for block-partitioned reconfigurable devices. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE). IEEE Computer Society, 10290-10295.
30. WALDER, H., STEIGER, C., AND PLATZNER, M. 2003. Fast online task placement on FPGAs: Free space partitioning and 2d-hashing. In Proceedings of the International Parallel and Distributed Processing Symposium. Vol. 17. IEEE Computer Society Press.