Beyond DVFS: A first look at performance under a hardware-enforced power bound

Proceedings of the 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2012

Volumn , Issue , 2012, Pages 947-953

  Rountree, Barry ^a   Ahn, Dong H ^a   De Supinski, Bronis R ^a   Lowenthal, David K ^b   Schulz, Martin ^a  

^a LAWRENCE LIVERMORE NATIONAL LABORATORY   (United States)

^b University of Arizona   (United States)

Author keywords

Power bound; RAPL

Indexed keywords

BALANCING POWER; CONTROL PROCESSORS; DYNAMIC VOLTAGE FREQUENCY SCALING; FIRST LOOK; HIGH-PERFORMANCE COMPUTING; MANUFACTURING VARIATION; NAS PARALLEL BENCHMARKS; POWER BOUND; PROCESSOR POWER; RAPL;

COMPUTER SOFTWARE SELECTION AND EVALUATION; DISTRIBUTED PARAMETER NETWORKS; HARDWARE; INTERCONNECTION NETWORKS;

PARALLEL PROCESSING SYSTEMS;

EID: 84867417218     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPSW.2012.116     Document Type: Conference Paper

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