Low-voltage ZnO double-gate thin film transistor circuits

Device Research Conference - Conference Digest, DRC

Volumn , Issue , 2012, Pages 239-240

  Li, Yuanyuan V ^a,b   Ramirez, J Israel ^a,b   Sun, Kaige G ^a,b   Jackson, Thomas N ^a,b  

^a Materials Research Institute   (United States)

^b The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT APPLICATION; DEVICE PERFORMANCE; DISPLAY TECHNOLOGIES; DOUBLE-GATE; FLEXIBLE POLYMERIC SUBSTRATES; GLASS SUBSTRATES; LARGE-AREA ELECTRONICS; LOGIC OPERATIONS; LOGIC TRANSITIONS; LOW VOLTAGE OPERATION; LOW VOLTAGES; LOW-VOLTAGE; MANUFACTURABILITY; PLASMA-ENHANCED ATOMIC LAYER DEPOSITION; PROCESS TEMPERATURE; PROPAGATION DELAYS; RING OSCILLATOR; THRESHOLD VOLTAGE TUNING; TOP GATE; ZNO; ZNO THIN FILM;

ATOMIC LAYER DEPOSITION; FIELD EFFECT TRANSISTORS; GATE DIELECTRICS; SUBSTRATES; THIN FILM TRANSISTORS; THRESHOLD VOLTAGE; ZINC OXIDE;

LOGIC CIRCUITS;

EID: 84866916651     PISSN: 15483770     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DRC.2012.6256969     Document Type: Conference Paper

References (5)

1. M. Halik, H. Klauk, U. Zschieschang, G. Schmid, C. Dehm, M. Schutz, S. Maisch, M. Brunnbauer, and F. Stellacci, Nature, 431, pp. 963-966 (2004).
2. S.Kyound-Seok, J. Ji-Sim, L. Kwang-Hee, K. Tae-Sang, P. Joon-Seok, P. KeeChan, K. Jang-Yeon, K. Bonwon, and L. Sang- Yoon, IEEE Elect. Dev. Lett., 31, pp. 812-814 (2010).
3. C. H. Park, K.H. Lee, M.S. Oh, K.Lee, S. Im, B.H. Lee, and M. M. Sung, IEEE Elect. Dev. Lett., 30, pp. 30-32 (2009).
4. D. A. Mourey, D. A. Zhao, and T. N. Jackson, IEEE Trans. Elect. Dev., 57, pp. 530-4 (2010).
5. D. A. Zhao, D.A. Mourey, and T. N. Jackson, IEEE Elect. Dev. Lett., 31, pp. 323-5 (2010).