Application of coreless substrate to package on package architectures

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2012, Pages 1368-1371

  Nickerson, Robert ^a   Olmedo, Reynaldo ^a   Mortensen, Russell ^a   Chee, Choong Kooi ^a   Goyal, Sanjay ^a   Low, Ai Ling ^a   Gealer, Charles ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTING PRODUCTS; DEVICE PERFORMANCE; DUAL CHANNEL; FORM FACTORS; HIGH PERFORMANCE APPLICATIONS; INTERCONNECT SCHEMES; MANUFACTURABILITY; PACKAGE TECHNOLOGIES; POWER DELIVERY; RELIABILITY PERFORMANCE; SIGNAL INTEGRITY; SIGNAL ROUTING; SILICON BUMPS; SILICON NODE; TABLET COMPUTER;

APPROXIMATION THEORY; ELECTRIC POWER TRANSMISSION; ELECTRONIC EQUIPMENT; SURFACE MOUNT TECHNOLOGY;

HAND HELD COMPUTERS;

EID: 84866839501     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2012.6249013     Document Type: Conference Paper

References (1)

1. JEDEC Standard, " Board Level Drop Test Method of Components for Handheld Electronic Products," JESD22-B111, July 2003