Pitfalls and Issues of Manycore Programming

Advances in Computers

Volumn 79, Issue C, 2010, Pages 71-117

  Marowka, Ami ^a  

^a BAR ILAN UNIVERSITY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 84866775652     PISSN: 00652458     EISSN: None     Source Type: Book Series    
DOI: 10.1016/S0065-2458(10)79002-1     Document Type: Chapter

References (68)

1. von Neumann, J., First Draft of a Report on EDVAC, 1945, Moore School of Electrical Engineering, University of Pennsylvania, Pennsylvania June 30.
2. Van Der Spiegel, J., Tau, J.F., Ala'illma, T.F., Ang, L.P., The ENIAC: History, operation and reconstruction in VLSI. Rojas, R., Hashagen, U., (eds.) The First Computers, History and Architectures, 2002, MIT press, Cambridge, MA, 121–178.
3. Aspray, W., The institute for advances study computer: A case study in the application of concepts from the history of technology. Rojas, R., Hashagen, U., (eds.) The First Computers, History and Architectures, 2002, MIT press, Cambridge, MA, 179–193.
4. Marcus, M., Akera, A., Exploring the architecture of early machine: The historical relevance of the ENIAC machine architecture. IEEE Ann. Hist. Comput. 18 (1996), 17–24.
5. Eckert, J.P., Mauchly, J.W., Goldstine, H.H., Brainerd, J.G., Description of the ENIAC and Comments on Electronic Digital Computing Machines, 1945, Moore School of Electrical Engineering, University of Pennsylvania, Pennsylvania November 30.
6. Marowka, A., Parallel computing on any desktop. Commun. ACM 50:9 (2007), 74–78.
7. OpenMP Architecture Review Board. OpenMP Application Program Interface, 2008 Version 3.0, May.
8. Chapman, B., Jost, G., van der Pas, R., Using OpenMP Portable Shared Memory Parallel Programming, 2007, MIT Press, Cambridge, MA.
9. Mattson, T., DeSouza, J., How Fast is Fast? Measuring and Understanding Parallel Performance, 2008 Intel Webinar.
10. Olukotun, K., Hammond, L., The future of microprocessors. ACM Queue, 2005, 27–34 September.
11. Sutter, H., The free lunch is over: A fundamental turn toward concurrency in software. Dr. Dobb's J. 30:3 (2005), 202–210.
12. Sutter, H., Larus, J., Software and the concurrency revolution. ACM Queue 3:7 (2005), 54–62.
13. Marowka, A., Think parallel: Teaching parallel programming today. IEEE Distrib. Syst. Online, 9(8), 2008.
14. Hambrush, S., Models for Parallel Computatio, Proceeding of ICPP Workshop on Challenges for Parallel Processing, 1996, 92–95.
15. Skillcorn, D., Talia, D., Models and languages for parallel computation. ACM Comput. Surv. 30:2 (1998), 123–169.
16. Culler, D., Karp, R., Patterson, D., Sahay, A., Schauser, K.E., Santos, E., Subramonian, R., von Eicken, T., LogP: Towards a realistic model of parallel computation. Proceeding of 4th ACMSIGPLAN Symposium on Principles and Practices of Parallel Programming, 1993, 1–12.
17. Valiant, L.G., A bridging model for parallel computation. Commun. of ACM 33:8 (1990), 103–111.
18. Bissling, H.R., Parallel Scientific Computation: A Structured Approach Using BSP and MPI, 2004, Oxford Press, Oxford.
19. Kuhn, T.S., The Structure of Scientific Revolutions, first Ed., 1962, University of Chicago Press, Chicago p. 168.
20. Parallel@Illinois. University of Illinois at Urbana-Champaign. http://www.parallel.illinois.edu/.
21. Pervasive Parallelism Laboratory at Stanford University. http://ppl.stanford.edu/wiki/index.php/Pervasive_Parallelism_Laboratory.
22. Parallel Computing Laboratory at Berkeley. http://parlab.eecs.berkeley.edu/about.html.
23. Asanovic, K., et al. The Landscape of Parallel Computing Research: A View from Berkeley, 2006, University of California, Berkeley, CA http://www.eecs.berkeley.edu/Pubs/TechRpts/2006/EECS-2006-183.html Technical Report No. UCB/EECS-2006-183, December 18.
24. http://www.highproductivity.org/.
25. Marowka, A., Portability of Parallel and Distributed Application, 2000, The Hebrew University of Jerusalem, Israel PhD Dissertation.
26. Marowka, A., Yarchi, I., Bercovier, M., Scalable portability evaluation of high performance applications. Int. J. Comput. Appl. 7:1 (2000), 39–47.
27. Marowka, A., Bercovier, M., A scalable portability model for parallel computing. J. Parallel Distrib. Comput. Pract. (PDCP) 3:3 (2000), 133–156.
28. Marowka, A., Portability of Parallel and Distributed Applications: Is it Possible to Build a Portable and Scalable Parallel Application?, 2009, VDM Verlag, Germany.
29. Brewer, E.A., High level optimization via automated statistical modeling. ACM SIGPLAN Notices, 30(8), 1995 Fifth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'95).
30. Brewer, E.A., Portable High-Performance Supercomputing: High-Level Platform-Dependent Optimization, 1994 MIT Ph.D. Dissertation, September.
31. Hey, T., Ferrante, J., Portability and Performance of Parallel Processing, 1994, Wiley, Chichester, NY.
32. Demmel, J., Dongarra, J., et al. Self-adapting linear algebra algorithms and software. Proc. IEEE 93:2 (2005), 293–312.
33. Skeletal Parallelism Homepage. www.dcs.ed.ac.uk/home/mic/skeletons.html.
34. Barret, R., Berry, M., Chan, T., Demmel, J., Donato, J., Dongarra, J., Pozo, V., Romine, C., Van, H., Templates for the Solution of Linear Systems: Building Blocks for Iterative Methods, 1993, SIAM, Philadelphia, PA www.netlib.org/utk/papers/etemplates/paper.html.
35. Feitelson, D.G., Rudolph, L., Toward convergence in job schedulers in parallel supercomputers. Feitelson, D.G., Rudolph, L., (eds.) Proceeding of the 2nd Workshop on Job Scheduling Strategies for Parallel Processing, 1996 April. LNCS 1162 (1996) 1–26. Springer, Berlin.
36. Merritt, R., HP calls for on-chip optics. EE Times, 2009 January.
37. LaPedus, M., Intel lists five challenges for IC scaling. EE Times, 2009 February.
38. Young, I., Mohammed, E., Liao, J., Kern, A., Palermo, S., Block, B., Reshotko, M., Chang, P., Optical I/O Technology for Tera-Scale Computing, International Solid State Circuits Conference (ISSCC), 2009.
39. Adl-Tabatabai, A., Kozyrakis, C., Saha, B., Unlocking concurrency. ACM Queue, 2007, 24–33, January.
40. Herlihy, M., Moss, E., Transactional memory: Architectural support for lock-free data structures. Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993 San Diego, CA, May.
41. Cantrill, B., Bonwick, J., Real-world concurrency. ACM Queue, 2008, 16–25, September.
42. Marowka, A., Empirical Analysis of Parallelism Overheads of CMPs, Proceeding of Eighth International Conference on Parallel Processing and Applied Mathematics (PPAM, September 2009, LNCS, Springer.
43. Olukotun, K., A Conversation with Hennessy and Patterson. ACM Queue, 2007, 14–22 January.
44. Dally, W.J., Patrick, B., Principles and Practices of Interconnection Networks Morgan Kaufmann Series in Computer Architecture and Design, 2004, Morgan Kaufmann, San Francisco, CA.
45. Kumar, V., Grama, A., Gupta, A., Karipis, G., Introduction to Parallel Computing, 1994, Benjamin/Cummings, Redwood City, CA.
46. Culler, D., Singh, J.P., Gupta, A., Parallel Computer Architecture: A Hardware/Software Approach Morgan Kaufmann Series in Computer Architecture and Design, 1998, Morgan Kaufmann, San Francisco, CA.
47. Akhter, S., Roberts, J., Multi-Core Programming: Increasing Performance Through Software Multithreading, 2006, Intel Press.
48. Mendelson, A., Mandelblat, J., Gochman, S., Shemer, A., Chabukswar, R., Niemeyer, E., Kumar, A., CMP implementation in systems based on the Intel Core Duo Processor. Intel Technology Journal, 10(2), 2006.
49. Marowka, A., Performance of OpenMP Benchmarks on Multicore Processors, 8th International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP) LNCS Proceeding, vol. 5022, 2008, 208–219 Agia Napa, Cyprus, June 9–11.
50. Knuth, D.E., Binstock, A., Interview with Donald Knuth, 2008, InformIT April 25.
51. Miles, D., Leback, B., Norton, D., Optimizing Application Performance on Cray Systems with PGI Compilers and Tools, Proceedings of CUG, 2006.
52. Intel Thread Checker. http://software.intel.com/en-us/intel-thread-checker/.
53. Intel Composer. http://software.intel.com/en-us/intel-parallel-composer/.
54. Allen, R., Kennedy, K., Optimizing Compilers for Modern Architectures: A Dependence-Based Approach, 2001, Morgan Kaufmann, San Francisco, CA.
55. Bernstein, A.J., Analysis of programs for parallel processing. IEEE Trans. Electron. Comput. 15:5 (1966), 757–763.
56. Lamport, L., How to make a multiprocessor computer that correctly executes multiprocess programs. IEEE Trans. Comput. C-28:9 (1979), 690–691.
57. Adve, S.V., Gharachorloo, K., Shared memory consistency models: A tutorial. IEEE Comput. 29:12 (1996), 66–76.
58. Dijkstra, E.W., Cooperating Sequential Processes, 1968, Academic Press, London Programming Languages.
59. Bull, M., O'Neill, D., Microbenchmark Suite for OpenMP 2.0, Proceedings of the Third European Workshop on OpenMP (EWOMP01), Barcelona, Spain, 2001, 41–48.
60. Lee, E.A., The Problem with Threads, 2006, Electrical Engineering and Computer Sciences, University of California, Berkeley Technical Report No. UCB/EECS-2006-1.
61. Vishkin, U., The PRAM-On-Chip Proof-of-Concept, 2009 Workshop on Theory and Many-Cores (T&MC).
62. Workshop on Theory and Many-Cores (T&MC). http://www.umiacs.umd.edu/conferences/tmc2009/, 2009 University of Maryland, College Park, Maryland, 2009, May 29.
63. Vishkin, U., Dascal, S., Berkovich, E., Nuzman, J., Explicit multi-threading (XMT) bridging models for instruction parallelism (extended abstract). Proc. 10th ACM Symposium on Parallel Algorithms and Architectures (SPAA), 1998 http://www.umiacs.umd.edu/users/vishkin/XMT/index.shtml.
64. Snir, M., et al. MPI: The Complete Reference, 1996, MIT Press, Cambridge, MA http://www.mcs.anl.gov/research/projects/mpi/.
65. Marowka, A., Think parallel: Teaching parallel programming today. IEEE Distrib. Syst. Online, 9(8), 2008.
66. Hennessy, J.L., Patterson, D.A., Computer Architecture, Fourth Ed: A Quantitative Approach, 2006, Morgan Kaufmann, San Francisco, CA.
67. Cormen, T., Leiserson, C., Rivest, R., Stein, C., Introduction to Algorithms, 2003, McGraw-Hill.
68. Holt, J., Agarwal, A., Brehmer, S., Domeika, M., Griffin, P., Schirrmeister, F., Software standards for the multicore era. IEEE Micro, 2009, 40–50 March/April.