A new 3-bit programming algorithm using SLC-to-TLC migration for 8MB/s high performance TLC NAND flash memory

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 2012, Pages 132-133

  Shin, Seung Hwan ^a   Shim, Dong Kyo ^a   Jeong, Jae Yong ^a   Kwon, Oh Suk ^a   Yoon, Sang Yong ^a   Choi, Myung Hoon ^a   Kim, Tae Young ^a   Park, Hyun Wook ^a   Yoon, Hyun Jun ^a   Song, Young Sun ^a   Choi, Yoon Hee ^a   Shim, Sang Won ^a   Ahn, Yang Lo ^a   Park, Ki Tae ^a   Han, Jin Man ^a   Kyung, Kye Hyun ^a   Jun, Young Hyun ^a  

^a SAMSUNG Electronics   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CONVENTIONAL METHODS; NAND FLASH; NAND FLASH MEMORY; PROGRAMMING ALGORITHMS;

NAND CIRCUITS; VLSI CIRCUITS;

ALGORITHMS;

EID: 84866604180     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIC.2012.6243825     Document Type: Conference Paper

References (4)

1. K.T. Park et al., ISSCC, 2011
2. Y.Li, et al., ISSCC, pp506-507, 2008
3. K.T. Park et al., IEEE J.Solid-State Circuits, pp.919-928, 2008
4. Trinh C. et al., ISSCC, pp. 246-247, 2009