Scalable 3-D vertical chain-cell-type phase-change memory with 4F2 poly-Si diodes

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 35-36

  Kinoshita, M ^a   Sasago, Y ^a   Minemura, H ^a   Anzai, Y ^a   Tai, M ^a   Fujisaki, Y ^a   Kusaba, S ^a   Morimoto, T ^a   Takahama, T ^a   Mine, T ^a   Shima, A ^a   Yonamoto, Y ^a   Kobayashi, T ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CELL SIZE; MEMORY ARRAY; MULTI-LAYERED; PHASE CHANGES; PROCESS STEPS; SCALING LIMITS; SINGLE-MASK; STACKED GATE; THREEDIMENSIONAL (3-D);

CYTOLOGY; FLASH MEMORY; PHASE CHANGE MEMORY; POLYSILICON;

CELLS;

EID: 84866561249     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242448     Document Type: Conference Paper

References (4)

1. R. Katsumata et al., Symp. on VLSI Tech., pp. 136-137 (2009).
2. Y. Sasago et al., Symp. on VLSI Tech., pp. 24-25 (2009).
3. Y. Sasago et al., Symp. on VLSI Tech., pp. 96-97 (2011).
4. Y. Yonamoto et al., Appl. Phys. Lett. 98 (2011) 103513.