Graphene interconnect lifetime under high current stress

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 121-122

  Chen, Xiangyu ^a   Seo, David H ^b   Seo, Sunae ^c   Chung, Hyunjong ^b   Wong, H S Philip ^a  

^a Stanford University   (United States)

^b Samsung Advanced Institute of Technology (SAIT)   (South Korea)

^c Sejong University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CONSTANT CURRENT STRESS; DEFECT FORMATION; HIGH CURRENT STRESS; STRESS CURRENT DENSITY;

GRAPHENE;

EID: 84866555549     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242491     Document Type: Conference Paper

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