Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 137-138

  Miki, H ^a   Yamaoka, M ^a   Frank, D J ^b   Cheng, K ^b   Park, D G ^b   Leobandung, E ^b   Torii, K ^c  

^a HITACHI AMERICA LTD   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

GATE VOLTAGES; LOGIC DELAYS; LOW POWER; NANO SCALE; RANDOM TELEGRAPH NOISE; RESPONSE PARAMETERS; TEMPERATURE DEPENDENCE;

NANOTECHNOLOGY;

EID: 84866551557     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242499     Document Type: Conference Paper

References (8)

1. K. Takeuchi et al, 2011 VLSI Tech., p.130.
2. S. O. Toh et al, 2011 VLSI Tech., p. 204.
3. M. Yamaoka et al, 2011 IEDM, p. 745.
4. H. Miki et al, 2010 IEDM, p.620.
5. K. Cheng et al, 2009 IEDM, p.49.
6. D. J. Frank, to be published in IRPS'12 (tutorial).
7. H. Miki et al, 2011 VLSI Tech., p. 146.
8. E. Cartier et al, 2006 IEDM, p. 321.