Understanding the feasibility of scaled III-V TFET for logic by bridging atomistic simulations and experimental results

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 183-184

  Avci, Uygar E ^a   Hasan, Sayed ^a   Nikonov, Dmitri E ^a   Rios, Rafael ^a   Kuhn, Kelin ^a   Young, Ian A ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMISTIC SIMULATIONS; DOUBLE-GATE; EXPERIMENTAL CHARACTERISTICS; EXPERIMENTAL DEVICES; FITTING PARAMETERS; GEOMETRY PARAMETER; LOGIC APPLICATIONS; LOW-VOLTAGE; PERFORMANCE IMPROVEMENTS; QUANTUM-MECHANICAL PREDICTIONS; THIN BODY;

QUANTUM THEORY;

FORECASTING;

EID: 84866550114     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242522     Document Type: Conference Paper

References (4)

1. U. Avci et al., VLSI Tech. (2011).
2. G. Dewey et al., IEDM Tech. Digest (2011).
3. M. Luisier et al., IEDM Tech. Digest (2009).
4. M. Luisier et al., Jour. Appl. Phys. (2010).