Development of ultra-thin chip-on-wafer process using bumpless interconnects for three-dimensional memory/logic applications

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 171-172

  Maeda, N ^a   Kitada, H ^a   Fujimoto, K ^c   Kim, Y S ^a   Kodama, S ^b   Yoshimi, S ^c   Akazawa, M ^c   Mizushima, Y ^d   Ohba, T ^a  

^a UNIVERSITY OF TOKYO   (Japan)

^b DISCO CORPORATION   (Japan)

^c DAI NIPPON PRINTING CO LTD   (Japan)

^d FUJITSU LABORATORIES LTD   (Japan)

Author keywords

3D IC; Bumpless contact and Off chip via; COW

Indexed keywords

COPPER REDISTRIBUTION; COW; GAP FILLING; OFF-CHIP; ORGANIC MATERIALS; STACKING STRUCTURES; ULTRA-THIN; VIA HOLE; VIA-FIRST; VOID FORMATION;

WAFER BONDING;

EID: 84866545728     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242516     Document Type: Conference Paper

References (6)

1. T. Ohba et al., Microelectronic Eng., Elsevier, 87 (3), 485 (2010)
2. N. Maeda et al., AMC 2008, MRS, 501 (2009)
3. H. Kitada et al., IEEE Proc. of IITC, 107 (2009)
4. Y. S. Kim et al., IEDM Tech. Dig., 365 (2009)
5. H. Kitada et al., Jpn. J. Appl. Phys., 50 (5), AD10033 (2011)
6. T. Ohba, Electrcochem. Soc. Trans., May 2012 in press