Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2012, Pages 157-158

  Kar, G S ^a   Fantini, A ^a   Chen, Y Y ^a,b   Paraschiv, V ^a   Govoreanu, B ^a   Hody, H ^a   Jossart, N ^a   Tielens, H ^a   Brus, S ^a   Richard, O ^a   Vandeweyer, T ^a   Wouters, D J ^a,b   Altimime, L ^a   Jurczak, M ^a  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CELL PERFORMANCE; HIGH DENSITY MEMORY; MANUFACTURABILITY; OPTIMIZED PROCESS; PROCESS IMPROVEMENT;

OPTIMIZATION;

SCALABILITY;

EID: 84866534395     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSIT.2012.6242509     Document Type: Conference Paper

References (4)

1. Cheng et al, IEDM Tech.Dig, pp. 448-451, 2010.
2. Govoreanu et al, IEDM Tech.Dig, pp. 729-732, 2011.
3. Kim et al, VLSI Symp, pp. 210-211, 2011.
4. Ho et al, IEDM Tech.Dig,pp. 436-439.