Modeling of power/ground plane noise in high speed digital electronics packaging

IEEE 2nd Topical Meeting on Electrical Performance of Electronic Packaging, EPEP 1993

Volumn , Issue , 1993, Pages 206-208

  Fang, J ^a   Liu, Y ^a   Chen, Y ^a   Wu, Z ^a   Agrawal, A ^b  

^a BINGHAMTON UNIVERSITY   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL ELECTROMAGNETICS; DIGITAL CIRCUITS;

ACCURATE MODELING; DELTA I-NOISE; ELECTROMAGNETIC MODELING; FULL WAVES; HIGH-SPEED DIGITAL ELECTRONICS; POWER AND GROUND PLANES;

ELECTRONICS PACKAGING;

EID: 84866352303     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPEP.1993.394553     Document Type: Conference Paper

References (4)

1. Rao R. Tummala and Eugene J. Rymaszewski, Microelectronics Packaging Handbook, Van Nostrand Reinhold, 1989.
2. R. Senthinathan and J. L. Prince, "Simultaneous Switching Noise Calculation for Packaged CMOS Devices, " IEEE J. Solid-state Circuit, vol. 11, Nev. 1991, pp. 1724-1728.
3. Ravi Kaw, David Yanaga and Farid Matta, "Multimetal DTAB Packages for a 125-MHz Computer", IEEE Tran. Comp., Hybrids, Manufact. Technol., vol. CHMT-16, pp. 95-112, Feb. 1993.
4. Wiren D. Becker and Raj Mittra, "FDTD Modeling of Noise in Computer packages, " 1993 IEEE Multi-Chip Module Conference, March 15-18, 1993, Santa Cruz, CA, pp. 123-127.