Scalable MapReduce framework on FPGA accelerated commodity hardware

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 7469 LNCS, Issue , 2012, Pages 280-294

  Yin, Dong ^a   Li, Ge ^a   Huang, Ke Di ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

Author keywords

FPGA; MapReduce framework; Scalability

Indexed keywords

CO-PROCESSORS; COMMODITY HARDWARE; COMPUTATION MODULES; COMPUTATION PROCESS; FPGA CHIPS; LOCAL MEMORIES; MAP-REDUCE; MODULE LIBRARY; SPECIAL HARDWARE; TASK-PROCESSING; WORKER NODES;

DATA PROCESSING; DISTRIBUTED COMPUTER SYSTEMS; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); INTERNET; PIPELINE PROCESSING SYSTEMS; SCALABILITY;

HARDWARE;

EID: 84866082512     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-32686-8_26     Document Type: Conference Paper

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