Reducing L1 caches power by exploiting software semantics

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 391-396

  Fang, Zhen ^a   Zhao, Li ^b   Jiang, Xiaowei ^b   Lu, Shih Lien ^b   Iyer, Ravi ^b   Li, Tong ^b   Lee, Seung Eun ^c  

^a NVIDIA   (United States)

^b INTEL CORPORATION   (United States)

^c Seoul National University of Science and Technology   (South Korea)

Author keywords

first level cache; ring level; simulation; virtual memory

Indexed keywords

ASSOCIATIVE SEARCH; CACHE BLOCKS; CACHE DESIGN; DATA CACHES; DYNAMIC POWER CONSUMPTION; FIRST-LEVEL CACHE; HARDWARE COST; HIGH PERFORMANCE PROCESSORS; IMPACT PERFORMANCE; INSTRUCTION CACHES; INSTRUCTION FETCH; MEMORY REFERENCES; MEMORY SPACE; PHYSICAL ADDRESS; SET-ASSOCIATIVE; SIMULATION; VIRTUAL MEMORY;

DESIGN; LOW POWER ELECTRONICS; OPTIMIZATION; SEMANTICS;

CACHE MEMORY;

EID: 84865550793     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333750     Document Type: Conference Paper

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