Process variation aware data management for STT-RAM cache design

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn , Issue , 2012, Pages 179-184

  Sun, Zhenyu ^a   Bi, Xiuyuan ^a   Li, Hai ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

Author keywords

mtj; process variation aware

Indexed keywords

CACHE ACCESS; CACHE DESIGN; CACHE ENERGY CONSUMPTION; DATA ACCESS; DATA BLOCKS; DESIGN PARAMETERS; FAST READ; HIGH DENSITY; INTERCONNECT LATENCY; MAGNETIC TECHNOLOGIES; MEMORY LOCATIONS; MISS-RATE; MTJ; ON CHIP MEMORY; PROCESS-VARIATION; RANDOM ACCESS MEMORIES; SPIN TRANSFER TORQUE; STANDBY POWER; TIME VARIATIONS;

DESIGN; INFORMATION MANAGEMENT; LOW POWER ELECTRONICS;

RANDOM ACCESS STORAGE;

EID: 84865539126     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2333660.2333706     Document Type: Conference Paper

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