A fault-tolerant architecture for parallel applications in tiled-CMPs

Journal of Supercomputing

Volumn 61, Issue 3, 2012, Pages 997-1023

  Sánchez, Daniel ^a   Aragón, Juan L ^a   García, José M ^a  

^a UNIVERSITY OF MURCIA   (Spain)

Author keywords

Fault tolerance; Parallel Systems; SMT architectures; Soft errors

Indexed keywords

ARCHITECTURAL SUPPORT; ATOMIC OPERATION; EXECUTION TIME; FAULT-TOLERANT; HARDWARE RELIABILITY; HARDWARE RESOURCES; MULTIMEDIA BENCHMARKS; PARALLEL APPLICATION; PARALLEL SYSTEM; RELIABLE EXECUTION; SCALING TECHNOLOGY; SHARED MEMORIES; SIMULTANEOUS MULTI-THREADING; SOFT ERROR; SUPPLY VOLTAGE REDUCTION; TEMPERATURE FLUCTUATION; TRANSIENT FAULTS;

ENERGY EFFICIENCY; FAULT DETECTION; FAULT TOLERANCE; MICROPROCESSOR CHIPS;

HARDWARE;

EID: 84865325391     PISSN: 09208542     EISSN: 15730484     Source Type: Journal    
DOI: 10.1007/s11227-011-0670-9     Document Type: Article

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