End-to-end sequential consistency

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 524-535

  Singh, Abhayendra ^a   Narayanasamy, Satish ^a   Marino, Daniel ^b   Millstein, Todd ^c   Musuvathi, Madanlal ^d  

^a UNIVERSITY OF MICHIGAN   (United States)

^b SYMANTEC RESEARCH LABS   (United States)

^c UNIVERSITY OF CALIFORNIA   (United States)

^d MICROSOFT RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MULTITASKING; PROGRAM COMPILERS;

COMPILER OPTIMIZATIONS; END TO END; HARDWARE OPTIMIZATION; LANGUAGE LEVELS; MULTI PROCESSOR SYSTEMS; MULTI-THREADED PROGRAMS; PERFORMANCE COSTS; PROGRAMMABILITY; SEQUENTIAL CONSISTENCY; SHARED MEMORY;

SEMANTICS;

EID: 84864839495     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2366231.2337220     Document Type: Conference Paper

References (55)

1. AMD Corporation. AMD-V Nested Paging. White paper. http://sites.amd.com/ us/business/itsolutions/virtualization/Pages/amd-v.aspx, 2008.
2. A.-R. Adl-Tabatabai and T. Gross. Source-Level Debugging of Scalar Optimized Code. In PLDI, 1996.
3. S. Adve. Designing Memory Consistency Models forShared-Memory Multiprocessors. PhD thesis, University of Wisconsin-Madison, 1993.
4. S. V. Adve and M. D. Hill. Weak Ordering-A New Definition. In ISCA, 1990.
5. S. V. Adve, M. D. Hill, B. P. Miller, and R. H. B. Netzer. Detecting Data Races on Weak Memory Systems. In ISCA, 1991.
6. W. Ahn, S. Qi, J.-W. Lee, M. Nicolaides, X. Fang, J. Torrellas, D. Wong, and S. Midkiff. BulkCompiler: High-Performance Sequential Consistency through Cooperative Compiler and Hardware Support. In MICRO, 2009.
7. P. Barford and M. Crovella. Generating Representative Web Workloads for Network and Server Performance Evaluation. In SIGMETRICS, 1998.
8. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC Benchmark Suite: Characterization and Architectural Implications. In PACT, 2008.
9. C. Blundell, M. Martin, and T. Wenisch. InvisiFence: Performance- Transparent Memory Ordering in Conventional Multiprocessors. In ISCA, 2009.
10. H. J. Boehm and S. V. Adve. Foundations of the C++ Concurrency Memory Model. In PLDI, 2008.
11. C. Boyapati, R. Lee, and M. Rinard. Ownership Types forSafe Programming: Preventing Data Races and Deadlocks. In OOPSLA, 2002.
12. C. Boyapati and M. Rinard. A Parameterized Type System for Race-Free Java Programs. In OOPSLA, 2001.
13. L. Ceze, J. Tuck, P.Montesinos, and J. Torrellas. BulkSC: Bulk Enforcement of Sequential Consistency. In ISCA, 2007.
14. Compaq Computer Corporation. Alpha 21264 MicroprocessorHardware Reference Manual. Order Number: EC-RJRZA-TE.
15. B. Cuesta, A. Ros, M. E. Gómez, A. Robles, and J. Duato. Increasing the Effectiveness of Directory Caches by Deactivating Coherence for Private Memory Blocks. In ISCA, 2011.
16. J. deok Choi, M. Gupta, M. J. Serrano, V. C, and S. P. Midkiff. Stack Allocation and Synchronization Optimizations for Java using Escape Analysis. ACM TOPLAS, 2003.
17. G. W. Dunlap, D. G. Lucchetti, M. Fetterman, and P. M. Chen. Execution Replay on Multiprocessor Virtual Machines. In VEE, 2008.
18. T. Elmas, S. Qadeer, and S. Tasiran. Goldilocks: A Race and Transaction-Aware Java Runtime. In PLDI, 2007.
19. The FeS2 simulator. http://fes2.cs.uiuc.edu/.
20. C. Flanagan and S. Freund. FastTrack: Efficient and precise dynamic race detection. In PLDI, 2009.
21. C. Flanagan and S. N. Freund. Type-Based Race Detection for Java. In PLDI, pages 219-232, 2000.
22. K. Gharachorloo, A. Gupta, and J. Hennessy. Two Techniques to Enhance the Performance of Memory Consistency Models. In ICPP, 1991.
23. C. Gniady and B. Falsafi. Speculative Sequential Consistency with Little Custom Storage. In PACT, 2002.
24. C. Gniady, B. Falsafi, and T. N. Vijaykumar. Is SC + ILP=RC? In ISCA, 1999.
25. L. Hammond, B. D. Carlstrom, V. Wong, B. Hertzberg, M. Chen, C. Kozyrakis, and K. Olukotun. Programming withTransactional Coherence and Consistency (TCC). In ASPLOS, 2004.
26. L. Hammond, V. Wong, M. K. Chen, B. D. Carlstrom, J. D. Davis, B. Hertzberg, M. K. Prabhu, H. Wijaya, C. Kozyrakis, and K. Olukotun. Transactional Memory Coherence and Consistency. In ISCA, 2004.
27. N. Hardavellas, M. Ferdman, B. Falsafi, and A. Ailamaki. Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches. In ISCA, 2009.
28. T. Harris, J. R. Larus, and R. Rajwar. Transactional Memory, 2nd edition. Synthesis Lectures on Computer Architecture. 2010.
29. M. Herlihy and J. E. B. Moss. Transactional Memory: Architectural Support for Lock-Free Data Structures. In ISCA, 1993.
30. M. D. Hill. Multiprocessors Should Support Simple Memory-Consistency Models. IEEE Computer, 31:28-34, 1998.
31. M. D. Hill, A. E. Condon, M. Plakal, and D. J. Sorin. A System-Level Specification Framework for I/O Architectures. In SPAA, 1999.
32. Intel® Corporation. Pentium® Pro Family Developer's Manual. 1996.
33. Intel® Corporation. Intel® 64 and IA-32 Architectures Optimization Reference Manual. Order Number: 248966-025, 2011.
34. A. Kamil, J. Su, and K. Yelick. Making Sequential Consistency Practical in Titanium. In ICS, 2005.
35. D. Kim, J. Ahn, J. Kim, and J. Huh. Subspace Snooping: Filtering Snoops with Operating System Support. In PACT, 2010.
36. L. Lamport. How toMake aMultiprocessor Computer that Correctly Executes Multiprocess Programs. IEEE Computer, 1979.
37. C. Lattner and V. Adve. LLVM: A Compilation Framework for Lifelong Program Analysis & Transformation. In CGO, 2004.
38. C. Lin, V. Nagarajan, and R. Gupta. Efficient SequentialConsistency Using Conditional Fences. In PACT, 2010.
39. C. Lin, V. Nagarajan, R. Gupta, and B. Rajaram. Efficient Sequential Consistency via Conflict Ordering. In ASPLOS, 2012.
40. B. Lucia, L. Ceze, K. Strauss, S. Qadeer, and H. Boehm. Conflict Exceptions: Providing Simple Parallel Language Semantics with Precise Hardware Exceptions. In ISCA, 2010.
41. J. Manson, W. Pugh, and S. V. Adve. The Java Memory Model. In POPL, 2005.
42. D. Marino, A. Singh, T. Millstein, M. Musuvathi, and S. Narayanasamy. DRFx: A Simple and Efficient Memory Model for Concurrent Programming Languages. In PLDI,2010.
43. D. Marino, A. Singh, T. Millstein, M. Musuvathi, and S. Narayanasamy. A Case for an SC-Preserving Compiler. In PLDI, 2011.
44. S. P.Midkiff, D. A. Padua, and R. Cytron. Compiling Programs with User Parallelism. In Selected papers of the second workshop on Languages and compilers for parallel computing, 1990.
45. A. Muzahid, D. Suarez, S. Qi, and J. Torrellas. SigRace: Signature-based Data Race Detection. In ISCA, 2009.
46. S. Narayanasamy, Z. Wang, J. Tigani, A. Edwards, and B. Calder. Automatically Classifying Benign and Harmful Data Races using Replay Analysis. In PLDI, 2007.
47. G. Neiger, A. Santoni, F. Leung, D. Rodgers, and R. Uhlig. Intel Virtualization Technology: Hardware Support for Efficient Processor Virtualization. Intel Technology Journal, 10(3), 2006.
48. M. Prvulovic and J. Torrelas. ReEnact: Using Thread- Level Speculation Mechanisms to Debug Data Races in Multithreaded codes. In ISCA, June 2003.
49. P. Ranganathan, V. Pai, and S. Adve. Using Speculative Retirement and Larger Instruction Windows to Narrow the Performance Gap between Memory Consistency Models. In SPAA, 1997.
50. A. Salcianu and M. Rinard. Pointer and escape analysis for multithreaded programs. In PPoPP, 2001.
51. D. Shasha and M. Snir. Efficient and Correct Execution of Parallel Programs that Share Memory. TOPLAS, 10(2), 1988.
52. A. Singh, D. Marino, S. Narayanasamy, T. Millstein, and M. Musuvathi. Efficient Processor Support for DRFx, a Memory Model with Exceptions. In ASPLOS, 2011.
53. Z. Sura, X. Fang, C. Wong, S. Midkiff, J. Lee, and D. Padua. Compiler Techniques for High Performance Sequentially Consistent Java Programs. In PPoPP, 2005.
54. T. Wenisch, A. Ailamaki, B. Falsafi, and A. Moshovos. Mechanisms for Store-wait-free Multiprocessors. In ISCA, 2007.
55. S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In ISCA, 1995.