TimeWarp: Rethinking timekeeping and performance monitoring mechanisms to mitigate side-channel attacks

Proceedings - International Symposium on Computer Architecture

Volumn , Issue , 2012, Pages 118-129

  Martin, Robert ^a   Demme, John ^a   Sethumadhavan, Simha ^a  

^a Columbia University ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FINE GRAINS; HARDWARE MODIFICATIONS; MITIGATION STRATEGY; PERFORMANCE COUNTERS; PERFORMANCE DEGRADATION; PERFORMANCE MONITORING; REFACTORINGS; SECURITY ATTACKS; SENSITIVE DATAS; SIDE CHANNEL ATTACK; SIDE-CHANNEL;

DEGRADATION; HARDWARE;

COMPUTER ARCHITECTURE;

EID: 84864837138     PISSN: 10636897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCA.2012.6237011     Document Type: Conference Paper

References (19)

1. Possible rdtsc bug - intel® software network. WWW page, 2009. http://software.intel.com/enus/forums/showthread.php?t=65593.
2. O. Aciiçmez. Yet another microarchitectural attack: Exploiting i-cache. In 14th ACM Conference on Computer and Communications Security (ACM CCS'07) Computer Security Architecture Workshop, 2007.
3. O. Aciiçmez, C. K. Koc, and J.-P. Seifert. On the power of simple branch prediction analysis. Cryptology ePrint Archive, Report 2006/351, 2006.
4. D. J. Bernstein. Cache-timing attacks on aes. Technical report, 2004. URL: http://cr.yp.to/papers.html/#cachetiming.
5. J. Demme and S. Sethumadhavan. Rapid identification of architectural bottlenecks via precise event counting. SIGA CH Comput. Archit. News, 39:353-364, June 2011.
6. J. L. Greathouse, Z. Ma, M. I. Frank, R. Peri, and T. Austin. Demand-driven software race detection using hardware performance counters. SIGARCH Comput. Archit. News, 39:165-176, June 2011.
7. D. Gullasch, E. Bangerter, and S. Krenn. Cache games - bringing access based cache attacks on aes to practice. In 2011 IEEE Symposium on Security and Privacy (SP), pages 490-505, May 2011.
8. D. Jayasinghe, J. Fernando, R. Herath, and R. R agel. R emote cache timing attack on advanced encryption standard and countermeasures. In Information and Automation for Sustainability (ICIAFs), 2010 5th International Conference on, pages 177 -182, dec. 2010.
9. S. L. Min and J.-D. Choi. An efficient cache-based access anomaly detection scheme. SIGPLAN Not., 26:235-244, April 1991.
10. A. Muzahid, D. Suárez, S. Qi, and J. Torrellas. Sigrace: signature-based data race detection. SIGARCH Comput. Archit. News, 37:337-348, June 2009.
11. M. Neve and J.-P. Seifert. Advances on access-driven cache attacks on aes. In Proceedings of the 13th international conference on Selected areas in cryptography, SAC'06, pages 147-162, Berlin, Heidelberg, 2007. Springer-Verlag.
12. D. A. Osvik, A. Shamir, and E. Tromer. Cache attacks and countermeasures: the case of aes. In Topics in Cryptology - CT-R SA 2006, The Cryptographers Track at the R SA Conference 2006, pages 1-20. Springer-Verlag, 2005.
13. D. Page. Partitioned cache architecture as a side-channel defence mechanism. Cryptology ePrint Archive, Report 2005/280, 2005.
14. C. Percival. Cache missing for fun and profit. In Proc. of BSDCan 2005, 2005.
15. M. Prvulovic and J. Torrellas. R eenact: using threadlevel speculation mechanisms to debug data races in multithreaded codes. In Proceedings of the 30th annual international symposium on Computer architecture, ISCA '03, pages 110-121, New York, NY, USA, 2003. ACM.
16. T. R istenpart, E. Tromer, H. Shacham, and S. Savage. Hey, you, get off of my cloud: exploring information leakage in third-party compute clouds. In Proceedings of the 16th ACM conference on Computer and communications security, CCS '09, pages 199-212, New York, NY, USA, 2009. ACM.
17. B. C. Vattikonda, S. Das, and H. Shacham. Eliminating fine grained timers in xen. In Proceedings of the 3rd ACM workshop on Cloud computing security workshop, CCSW '11 pages 41-46, New York, NY, USA, 2011. ACM.
18. Z. Wang and R. Lee. A novel cache architecture with enhanced performance and security. In Microarchitecture, 2008. MICRO-41. 2008 41st IEEE/ACM International Symposium on, pages 83 -93, nov. 2008.
19. Z. Wang and R. B. Lee. New cache designs for thwarting software cache-based side channel attacks. SIGAR CH Comput. Archit. News, 35:494-505, June 2007.