Versatile refresh: Low complexity refresh scheduling for high-throughput multi-banked eDRAM

Performance Evaluation Review

Volumn 40, Issue 1 SPEC. ISS., 2012, Pages 247-258

  Alizadeh, Mohammad ^a   Javanmard, Adel ^a   Chuang, Shang Tse ^b   Iyer, Sundar ^b   Lu, Yi ^c  

^a STANFORD UNIVERSITY   (United States)

^b Memoir Systems   (United States)

^c UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

embedded DRAM; memory refresh scheduling; multi banked

Indexed keywords

ACCESS PATTERNS; CASE MEMORY; CONCURRENT REFRESH MODE; CONVENTIONAL TECHNIQUES; DATA INTEGRITY; DATA RETENTION; DATA RETENTION TIME; EMBEDDED DRAM; HIGH PERFORMANCE SYSTEMS; HIGH-THROUGHPUT; IDLE CYCLES; LOW-COMPLEXITY; MEMORY ACCESS; MEMORY ACCESS PATTERNS; MEMORY BANKS; MEMORY CELL; MULTI-BANKED; RETENTION TIME; SUFFICIENT CONDITIONS; SYNTHETIC BENCHMARK; VARIABLE PERFORMANCE; WRITE OPERATIONS;

ALGORITHMS; COMMERCE; EMBEDDED SYSTEMS; OPTIMIZATION; SCHEDULING;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 84864699752     PISSN: 01635999     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2254756.2254787     Document Type: Conference Paper

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