Optimizing video application design for phase-change RAM-based main memory

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 11, 2012, Pages 2011-2019

  Kwon, Suknam ^a   Yoo, Sungjoo ^a   Lee, Sunggu ^a   Park, Jinpyo ^b  

^a Pohang University of Science and Technology (POSTECH)   (South Korea)

^b SAMSUNG Electronics   (South Korea)

Author keywords

Data encoding; differential writes; phase change RAM (PRAM); write endurance

Indexed keywords

DATA ENCODING; DIFFERENTIAL DATA; DIFFERENTIAL WRITES; INTER-FRAME; MAIN MEMORY; MEMORY TECHNOLOGY; PHASE CHANGES; PHASE-CHANGE RAM; TRAFFIC DEMANDS; VIDEO APPLICATIONS; VIDEO CODECS;

DESIGN; DURABILITY; ENCODING (SYMBOLS); OPTIMIZATION;

RANDOM ACCESS STORAGE;

EID: 84864584556     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2165974     Document Type: Article

References (27)

1. U. Rosso, "Phase change memory technology overview," presented at the Emerg. Memory Technol., Saint-Malo, France, 2010.
2. M. Abdulla and M. Greenberg, "Will phase change memory (PCM) replace DRAM or NAND flash?," presented at the Flash Memory Summit, Santa Clara, CA, 2010.
3. Numonyx, Boise, ID, "Phase change memory (PCM): A new memory technology to enable new memory usage models," 2009.
4. [Online]. Available: www.numonyx.com/en-us/MemoryProducts/PCM/Pages/PCM. aspx
5. Micron Tech., Inc., Boise, ID, "Numonyx launches low-cost, low-power DDR interface non-volatile RAM products," 2008.
6. [Online]. Available: http://news. micron.com/releasedetail. cfm?ReleaseID= 467779
7. C. Villa, D. Mills, G. Barkley, H. Giduturi, S. Schippers, and D. Vimercati, "A 45 nm 1 Gb 1. 8 V phase-change memory," in Proc. ISSCC, 2010, pp. 270-271.
8. ITRS, "International Technology Roadmap for Semiconductors (ITRS)," 2007. [Online]. Available: www.itrs.net
9. T. Nirschl, J. B. Philipp, T. D. Happ, G. W. Burr, B. Rajendran, M. H. Lee, A. Schrott, M. Yang, M. Breitwisch, C. F. Chen, E. Joseph, M. Lamorey, R. Cheek, S. H. Chen, S. Zaidi, S. Raoux, Y. C. Chen, Y. Zhu, R. Bergmann, H. L. Lung, and C. Lam, "Write strategies for 2 and 4-bit multi-level phase-change memory," in Proc. Int. Electron Devices Meet. (IEDM), 2007, pp. 461-464.
10. M. Ghosh and H. S. Lee, "Smart refresh: An enhanced memory controller design for reducing energy in conventional and 3D die-stacked DRAMs," in Proc. Int. Symp. Microarch. (MICRO), 2007, pp. 1-2.
11. B. C. Lee, E. Ipek, O. Mutlu, and D. Burger, "Architecting phase change memory as a scalable DRAM alternative," in Proc. Int. Symp. Comput. Arch. (ISCA), 2009, pp. 10-12.
12. M. K. Qureshi, V. Srinivasan, and J. A. Rivers, "Scalable high performancemainmemory systemusing phase-changememory technology," in Proc. Int. Symp. Comput. Arch. (ISCA), 2009, pp. 24-33.
13. P. Zhou, B. Zhao, J. Yang, and Y. Zhang, "A durable and energy efficient main memory using phase change memory technology," in Proc. Int. Symp. Comput. Arch. (ISCA), 2009, pp. 2-6.
14. B. D. Yang, J. E. Lee, J. S. Kim, and J. Cho, "A low power phase-change random access memory using a data-comparison write scheme," in Proc. Int. Symp. Circuits Syst. (ISCAS), 2007, pp. 3014-3017. (Pubitemid 47449183)
15. S. Cho and H. Lee, "Flit-N-write: A simple deterministic technique to improve PRAM write performance, energy and endurance," in Proc. Int. Symp. Microarch. (MICRO), 2009, pp. 347-357.
16. W. Xu, J. Liu, and T. Zhang, "Data manipulation technique to reduce phase change memory write energy," in Proc. Int. Symp. Low Power Electron. Design (ISLPED), 2009, pp. 238-241.
17. N. H. Seong, D. H. Woo, and H. S. Lee, "Security refresh: Prevent malicious wear-out and increase durability for phase-change memory with dynamically randomized address mapping," in Proc. Int. Symp. Comput. Arch. (ISCA), 2010, pp. 384-393.
18. S. Schechter,G. H. Loh, K. Strauss, andD. Burger, "Use ECP, not ECC, for hard failures in resistive memories," in Proc. Int. Symp. Comput. Arch. (ISCA), 2010, pp. 2-11.
19. E. Ipek, J. Condit, E. B. Nightingale, D. Burger, and T. Moscibroda, "Dynamically replicated memory: Building reliable systems from nanoscale resistive memories," in Proc. Int. Conf. Arch. Support for Program. Lang. Operat. Syst. (ASPLOS), 2010, pp. 5-13.
20. G. Dhiman, R. Ayoub, and T. Rosing, "PDRAM: A hybrid PRAM and DRAM main memory system," in Proc. Design Autom. Conf. (DAC), 2009, pp. 2-6.
21. M. K. Qureshi, J. Karidis, and M. Franceschini, "Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling," in Proc. Int. Symp. Microarch. (MICRO), 2009, pp. 3-9.
22. A. P. Ferreira, M. Zhou, S. Bock, B. Childers, R. Melhem, and D. Mosse, "Increasing PCM main memory lifetime," in Proc. Design Autom. Test Euro. (DATE), 2010, pp. 2-4.
23. M. R. Stan andW. P. Burleson, "Bus-invert coding for low-power I/O," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 3, no. 1, pp. 49-58, Mar. 1995.
24. K. Lee, B. Cho, W. Cho, S. Kang, B. Choi, H. Oh, C. Lee, H. Kim, J. Park, Q. Wang, Y. Ro, J. Choi, K. Kim, Y. Kim, I. Shin, K. Lim, H. Cho, C. Choi, W. Chung, D. Kim, Y. Yoon, K. Yu, G. Jeong, H. Jeong, C. KimKwak, C. Kim, and K., "A 90 nm 1. 8 V 512 Mb diode-switch PRAM with 266 MB/s read throughput," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 150-162, Jan. 2008.
25. Video Clips. [Online]. Available: http://media. xiph.org/video/derf/
26. N. Seong, D. Woo, V. Srinivassan, J. A. Rivers, and H. S. Lee, "SAFER: Stuck-At-fault error recovery for memories," in Proc. Int. Symp. Microarch. (MICRO), 2010, pp. 2-7.
27. H. Chung, B. Jeong, B. Min, Y. Choi, B. Cho, J. Shin, J. Kim, S. Jung, J. Park, Q. Wang, Y. Lee, S. Cha, D. Kwon, S. Kim, S. Kim, Y. Rho, M. Park, J. Kim, I. Song, S. Jun, J. Lee, K. Kim, K. Lim,W. Chung, C. Choi, H. Cho, I. Shin, W. Jun, S. Hwang, K. Song, K. Lee, S. Chang, W. Cho, J. Yoo, and Y. Jun, "A 58 nm 1. 8 V 1 Gb PRAM with 6. 4 MB/s program BW," in Proc. Int. Solid-State Circuits Conf. (ISSCC), 2011, pp. 500-502.