A 4-GHz all digital PLL with low-power TDC and phase-error compensation

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 59, Issue 8, 2012, Pages 1706-1719

  Lee, Ja Yol ^a   Park, Mi Jeong ^a   Min, Byung Hun ^a   Kim, Seongdo ^a   Park, Mun Yang ^a   Yu, Hyun Kyu ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

ADPLL; DCO; loop settling monitor; metastability; phase noise; phase error compensator; settling time; TDC

Indexed keywords

CLOCKS; ERROR COMPENSATION; ERROR CORRECTION; PHASE LOCKED LOOPS;

ADPLL; HIGH SPEED ACCUMULATORS; IN-BAND PHASE NOISE; METASTABILITIES; PHASE ERROR; PHASE ERROR COMPENSATIONS; PHASE ERROR CORRECTION; SETTLING TIME;

PHASE NOISE;

EID: 84864572300     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2012.2206500     Document Type: Article

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