Hybrid chip-scale optical interconnects using multiple quantum well devices bonded to silicon

2012 Optical Interconnects Conference, OIC 2012

Volumn , Issue , 2012, Pages 18-19

  Nair, Rohit ^a   Gu, Tian ^a   Haney, Michael W ^a  

^a UNIVERSITY OF DELAWARE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP-SCALE; CONTRAST RATIO; GRAY-SCALE LITHOGRAPHY; LINK PERFORMANCE; OPTICAL INTERCONNECT;

SEMICONDUCTOR QUANTUM WELLS;

OPTICAL INTERCONNECTS;

EID: 84864259200     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OIC.2012.6224469     Document Type: Conference Paper

References (4)

1. M. W. Haney, et. al., "Chip-scale Integrated Optical Interconnects - A Key Enabler for Future High Performance Computing," Proc. SPIE 8267, 2012.
2. K. W. Goossen, et. al., "GaAs MQW modulators integrated with silicon CMOS," IEEE Photonics Technology Letters 7(4), 360-362, 1995.
3. R. Nair, et. al., "Demonstration of chip-scale optical interconnects based on the integration of polymer waveguides and multiple quantum well modulators on silicon," Proc. IEEE Photonics 2011 Conference, 2011.
4. T. Gu, et. al., "On-chip guided-wave optical interconnects using multiple quantum well modulators," Proc. IEEE Photonics 2011 Conference, 2011.