Model checking SDL with spin

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 1785 LNCS, Issue , 2000, Pages 363-377

  Bošnački, Dragan ^a   Dams, Dennis ^a   Holenderski, Leszek ^a   Sidorova, Natalia ^a  

^a EINDHOVEN UNIVERSITY OF TECHNOLOGY   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

ARTIFICIAL INTELLIGENCE; COMPUTER SCIENCE; COMPUTERS;

FRONT END; INDUSTRIAL PROTOCOLS; MODEL CHECKER; NON-TRIVIAL; PROMELA; SDL-MODEL; TIMING PROPERTIES; TOOLSETS;

MODEL CHECKING;

EID: 84863904536     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/3-540-46419-0_25     Document Type: Conference Paper

References (13)

1. R. Alur, D.L. Dill, A Theory of Timed Automata, Theoretical Computer Science, 126, pp. 183-235, 1994.
2. D. Bošnački, D. Dams, Integrating Real Time into Spin: A Prototype Implementation, S. Budkowski, A. Cavalli, E. Najm, editors, Formal Description Techniques and Protocol Specification, Testing and Verification (FORTE/PSTV'98), Kluwer, 1998.
3. M. Bozga, J-C. Fernandez, L. Ghirvu, S. Graf, J.P. Karimm, L. Mounier, J. Sifakis, If: An Intermediate Representation for SDL and its Applications, In Proc. of SDL-FORUM'99, Montreal, Canada, 1999.
4. I. Dravapoulos, N. Pronios, S. Denazis et al., The Magic WAND, Deliverable 3D2, Wireless ATM MAC, September 1997.
5. G. J. Holzmann, Design and Validation of Communication Protocols, Prentice Hall, 1991. Also: http://netlib.bell-labs.com/netlib/spin/whatispin. html
6. G.J. Holzmann, J. Patti, Validating SDL Specification: an Experiment, In E. Brinksma, G. Scollo, Ch.A. Vissers, editors, Protocol Specification, Testing and Verification, Enchede, The Netherlands, 6-9 June 1989, pp. 317-326, Amsterdam, 1990. North-Holland.
7. G.J. Holzmann, D. Peled, An Improvement of Formal Verification, PSTV 1994 Conference, Bern, Switzerland, 1994.
8. A. Olsen et al., System Engineering Using SDL-92, Elsevier Science, North-Holland, 1997.
9. D. Peled, Combining Partial Order Reductions with On-the-Fly Model Checking, Computer Aided Verification CAV 94, LCNS 818, pp. 377-390, 1994.
10. H. Tuominen, Embedding a Dialect of SDL in PROMELA, 6th Int. SPIN Workshop, LNCS 1680, pp. 245-260, 1999.
11. Verilog, Object GEODE tutorial, Version 1.2, Verilog SA, Toulouse, France, 1996.
12. VIRES, Verifying Industrially Relevant Systems, Esprit Long Term Research Project #23498, http://radon.ics.ele.tue.nl/~vires, 1996.
13. WAND consortium, Magic WAND - Wireless ATM Network Demonstrator, http://www.tik.ee.ethz.ch/~wand, 1996.