Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers

Neural Networks

Volumn 33, Issue , 2012, Pages 42-57

  Carrillo, Snaider ^a   Harkin, Jim ^a   McDaid, Liam ^a   Pande, Sandeep ^b   Cawley, Seamus ^b   McGinley, Brian ^b   Morgan, Fearghal ^b  

^a UNIVERSITY OF ULSTER   (United Kingdom)

^b NATIONAL UNIVERSITY OF IRELAND   (Ireland)

Author keywords

Adaptive router; Brain inspired computing; Fault tolerant; Inter neuron scalability; Network on chip; Spiking neural networks

Indexed keywords

ADAPTIVE ROUTERS; BRAIN-INSPIRED; FAULT-TOLERANT; NETWORK ON CHIP; SPIKING NEURAL NETWORKS;

CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; DATA PROCESSING; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HARDWARE; INTELLIGENT AGENTS; NEURAL NETWORKS; NEURONS; SCALABILITY; SERVERS; TRAFFIC CONGESTION; VLSI CIRCUITS;

ROUTERS;

ADAPTIVE NETWORK ON CHIP ROUTER; ARTICLE; ARTIFICIAL NEURAL NETWORK; COMPUTER; FEASIBILITY STUDY; PRIORITY JOURNAL; TECHNOLOGY; TELECOMMUNICATION;

ACTION POTENTIALS; ADAPTATION, PHYSIOLOGICAL; BRAIN; HUMANS; NEURAL NETWORKS (COMPUTER);

EID: 84863874825     PISSN: 08936080     EISSN: 18792782     Source Type: Journal    
DOI: 10.1016/j.neunet.2012.04.004     Document Type: Article

References (42)

1. Agarwal A., Iskander C., Shankar R. Survey of network on chip (noc) architectures & contributions. Journal of Engineering, Computing and Architecture 2009, 3:21-27.
2. Ajima Y., Sumimoto S., Shimizu T. Tofu: A 6d mesh/torus interconnect for exascale computers. Computer 2009, 42:36-40.
3. Benini L., De Micheli G. Networks on chips: a new soc paradigm. Computer 2002, 35:70-78.
4. Bjerregaard T., Mahadevan S. A survey of research and practices of network-on-chip. ACM Computing Surveys 2006, 38.
5. Boura, Y., & Das, C. (1994). Efficient fully adaptive wormhole routing in n-dimensional meshes. In Distributed computing systems, 1994., proceedings of the 14th international conference on (pp. 589-596).
6. Carrillo S., Harkin J., McDaid L., Pande S., Cawley S., Morgan F. Adaptive routing strategies for large scale spiking neural network hardware implementations. Proceedings of the 21th international conference on artificial neural networks - volume part I ICANN'11 2011, 77-84. Springer-Verlag, Berlin, Heidelberg.
7. Carrillo S., Harkin J., McDaid L., Pande S., Morgan F. An efficient, high-throughput adaptive noc router for large scale spiking neural network hardware implementations. Proceedings of the 9th international conference on evolvable systems: from biology to hardware ICES'10 2010, 133-144. Springer-Verlag, Berlin, Heidelberg.
8. Cawley S., Morgan F., McGinley B., Pande S., McDaid L., Carrillo S., et al. Hardware spiking neural network prototyping and application. Genetic Programming and Evolvable Machines 2011, 12:257-280.
9. Chen, Y., McDaid, L., Hall, S., & Kelly, P. (2008). A programmable facilitating synapse device. In Neural networks, 2008. IJCNN 2008. (IEEE world congress on computational intelligence). IEEE international joint conference on(pp. 1615-1620).
10. Chiu G.-M. The odd-even turn model for adaptive routing. Parallel and Distributed Systems, IEEE Transactions on 2000, 11:729-738.
11. Dally W., Towles B. Principles and practices of interconnection networks 2004, Morgan Kaufmann.
12. de Garis H., Shuo C., Goertzel B., Ruiting L. A world survey of artificial brain projects, part i: large-scale brain simulations. Neurocomputing 2010, 74:3-29. Artificial Brains.
13. Duato J., Yalamanchili S., Ni L. Interconnection networks: an engineering approach 2003, Morgan Kaufmann.
14. Furber, S., & Brown, A. (2009). Biologically-inspired massively-parallel architectures - computing beyond a million processors. In Application of concurrency to system design, 2009. ACSD '09. Ninth international conference on (pp. 3-12).
15. Furber S., Temple S. Neural systems engineering. Journal of the Royal Society interface 2007, 4:193.
16. Furber, S., Temple, S., & Brown, A. (2006). High-performance computing for systems of spiking neurons. In AISB06 workshop on GC5: architecture of brain and mind (pp. 29-36). Vol. 2.
17. Gerstner W., Kistler W. Spiking neuron models: single neurons, populations, plasticity 2002, Cambridge Univ Pr.
18. Hale K.C., Grot B., Keckler S.W. Segment gating for static energy reduction in networks-on-chip. Proceedings of the 2nd international workshop on network on chip architectures NoCArc '09 2009, 57-62. ACM, New York, NY, USA.
19. Harkin J., Morgan F., McDaid L., Hall S., McGinley B., Cawley S. A reconfigurable and biologically inspired paradigm for computation using network-on-chip and spiking neural networks. International Journal of Reconfigurable Computing 2009, 2009:1-13.
20. Hylton, T. (2008). Systems of neuromorphic adaptive plastic scalable electronics. In DARPA SYNAPSE bidders workshop and teaming meeting.
21. Izhikevich E. Which model to use for cortical spiking neurons?. Neural Networks, IEEE Transactions on 2004, 15:1063-1070.
22. Izhikevich E. Simple model of spiking neurons. Neural Networks, IEEE Transactions on 2003, 14:1569-1572.
23. Jain A., Mao J., Mohiuddin K. Artificial neural networks: a tutorial. Computer 1996, 29:31-44.
24. Jin X., Lujan M., Plana L., Davies S., Temple S., Furber S. Modeling spiking neural networks on spinnaker. Computing in Science Engineering 2010, 12:91-97.
25. Livi, P., & Indiveri, G. (2009). A current-mode conductance-based silicon neuron for address-event neuromorphic systems. In Circuits and systems, 2009. ISCAS 2009. IEEE international symposium on (pp. 2898-2901).
26. Maass W. Networks of spiking neurons: the third generation of neural network models. Neural Networks 1997, 10:1659-1671.
27. Maguire L., McGinnity T., Glackin B., Ghani A., Belatreche A., Harkin J. Challenges for large-scale implementations of spiking neural networks on fpgas. Neurocomputing 2007, 71:13-29. Dedicated hardware architectures for intelligent systems; advances on neural networks for speech and audio processing.
28. Markram H. The blue brain project. Nature Reviews Neuroscience 2006, 7:153-159.
29. Misra J., Saha I. Artificial neural networks in hardware: a survey of two decades of progress. Neurocomputing 2010, 74:239-255. Artificial Brains.
30. Nageswaran, J., Dutt, N., Krichmar, J., Nicolau, A., & Veidenbaum, A. (2009). Efficient simulation of large-scale spiking neural networks using cuda graphics processors. In Neural networks, 2009. IJCNN 2009. International joint conference on (pp. 2145-2152).
31. Palesi M., Kumar S., Catania V. Bandwidth-aware routing algorithms for networks-on-chip platforms. Computers Digital Techniques, IET 2009, 3:413-429.
32. Pande, S., Morgan, F., Cawley, S., McGinley, B., Carrillo, S., & Harkin, J. et al. (2010). Embrace-sysc for analysis of noc-based spiking neural network architectures. In System on chip (SoC), 2010 international symposium on (pp. 139-145).
33. Paugam-Moisy H., Bohte S. Computing with spiking neuron networks. Handbook of natural computing 2009, 40. Springer, Heidelberg.
34. Plana L., Furber S., Temple S., Khan M., Shi Y., Wu J., et al. A gals infrastructure for a massively parallel multiprocessor. Design Test of Computers, IEEE 2007, 24:454-463.
35. Roche B., Mc Ginnity T., Maguire L., Mc Daid L. Signalling techniques and their effect on neural network implementation sizes. Information Sciences 2001, 132:67-82.
36. Schemmel, J., Fieres, J., & Meier, K. (2008). Wafer-scale integration of analog neural networks. In Neural networks, 2008. IJCNN 2008. (IEEE world congress on computational intelligence) IEEE international joint conference on (pp. 431-438).
37. Shayani H., Bentley P., Tyrrell A. A cellular structure for online routing of digital spiking neuron axons and dendrites on fpgas. Lecture notes in computer science 2008, Vol. 5216:273-284. Springer, Berlin, Heidelberg. G. Hornby, L. Sekanina, P. Haddow (Eds.).
38. Smith L. Implementing neural models in silicon. Handbook of Nature-Inspired and Innovative Computing 2006, 433-475.
39. Theocharides, T., Link, G., Vijaykrishnan, N., Invin, M., & Srikantam, V. (2004). A generic reconfigurable neural network architecture as a network on chip. In SOC conference, 2004. Proceedings. IEEE international (pp. 191-194).
40. Thomas, D., & Luk, W. (2009). Fpga accelerated simulation of biologically plausible spiking neural networks. In Field programmable custom computing machines, 2009. FCCM '09. 17th IEEE symposium on (pp. 45-52).
41. Trappenberg T. Fundamentals of computational neuroscience 2010, Oxford Univ Pr.
42. Wade, J. (2010). A biologically inspired training algorithm for spiking neural networks. Ph.D. thesis, University of Ulster.