Future cache design using STT MRAMs for improved energy efficiency: Devices, circuits and architecture

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 492-497

  Park, Sang Phill ^a   Gupta, Sumeet ^a   Mojumder, Niladri ^a   Raghunathan, Anand ^a   Roy, Kaushik ^a  

^a PURDUE UNIVERSITY   (United States)

Author keywords

cache; emerging devices; memory; spin; STT MRAM

Indexed keywords

CACHE; CACHE DESIGN; CIRCUIT LEVELS; COMPUTING PLATFORM; CROSS-LAYER; EMERGING DEVICES; ENERGY EFFICIENT; MAGNETIC RAMS; NONVOLATILITY; ON CHIP MEMORY; SPIN; SPIN TRANSFER TORQUE; STT MRAM;

CACHE MEMORY; COMPUTER AIDED DESIGN; DATA STORAGE EQUIPMENT; ENERGY EFFICIENCY; MAGNETIC DEVICES; STATIC RANDOM ACCESS STORAGE;

MRAM DEVICES;

EID: 84863554409     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228447     Document Type: Conference Paper

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