A QoS-aware memory controller for dynamically balancing GPU and CPU bandwidth use in an MPSoC

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 850-855

  Jeong, Min Kyu ^a   Erez, Mattan ^a   Sudanthi, Chander ^b   Paver, Nigel ^b  

^a The University of Texas at Austin   (United States)

^b ARM Inc   (United States)

Author keywords

graphics processor; memory controller; quality of service; system on chip

Indexed keywords

GRAPHICS PROCESSOR; HIGH BANDWIDTH; IP CORE; MEMORY CONTROLLER; OFF-CHIP MEMORIES; SYSTEM ON CHIPS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMPUTER AIDED DESIGN; MICROPROCESSOR CHIPS;

QUALITY OF SERVICE;

EID: 84863550145     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228513     Document Type: Conference Paper

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