Automatic speculative DOALL for clusters

Proceedings - International Symposium on Code Generation and Optimization, CGO 2012

Volumn , Issue , 2012, Pages 94-103

  Kim, Hanjun ^a   Johnson, Nick P ^a   Lee, Jae W ^b   Mahlke, Scott A ^c   August, David I ^a  

^a PRINCETON UNIVERSITY   (United States)

^b Sungkyunkwan University   (South Korea)

^c UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATIC PARALLELIZATION; COMMUNICATION PATTERN; DISTRIBUTED MEMORY CLUSTERS; ERROR PRONES; HIGH BANDWIDTH; PARALLELIZATIONS; PARALLELIZING COMPILER; RUNTIMES; SOURCE CODES; SPECULATIVE PARALLELIZATION;

NETWORK COMPONENTS; OPTIMIZATION; STATIC ANALYSIS;

PROGRAM COMPILERS;

EID: 84863500114     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2259016.2259029     Document Type: Conference Paper

References (25)

1. S. P. Amarasinghe and M. S. Lam. Communication optimization and code generation for distributed memory machines. In Proceedings of the ACM SIGPLAN 1993 conference on Programming language design and implementation, 1993.
2. C. Bienia, S. Kumar, J. P. Singh, and K. Li. The PARSEC benchmark suite: characterization and architectural implications. In Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques (PACT), 2008.
3. B. Blume, R. Eigenmann, K. Faigin, J. Grout, J. Hoef inger, D. Padua, P. Petersen, B. Pottenger, L. Rauchwerger, P. Tu, and S. Weatherford. Polaris: The next generation in parallelizing compilers. In Proceedings of the Workshop on Languages and Compilers for Parallel Computing, 1994.
4. R. L. Bocchino, V. S. Adve, and B. L. Chamberlain. Software transactional memory for large scale clusters. In PPoPP'08: Proceedings of the 13th ACM SIGPLAN Symposium on Principles and practice of parallel programming, 2008.
5. C. Cascaval, C. Blundell, M. Michael, H. W. Cain, P. Wu, S. Chiras, and S. Chatterjee. Software transactional memory: Why is it only a research toy? Queue, 6(5):46-58, 2008.
6. M. Couceiro, P. Romano, N. Carvalho, and L. Rodrigues. D2STM: Dependable distributed software transactional memory. Pacif c Rim International Symposium on Dependable Computing, IEEE, 0:307-313, 2009.
7. J. P. Hoef inger. Extending OpenMP to clusters. White Paper Intel Corporation, 2006.
8. H. Kim, A. Raman, F. Liu, J. W. Lee, and D. I. August. Scalable speculative parallelization on commodity clusters. In In Proceedings of the 43rd IEEE/ACM International Symposium on Microarchitecture, 2010.
9. C. Kotselidis, M. Ansari, K. Jarvis, M. Luján, C. Kirkham, and I. Watson. DiSTM: A software transactional memory framework for clusters. In ICPP'08: Proceedings of the 2008 37th International Conference on Parallel Processing, 2008.
10. C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In CGO'04: Proceedings of the International Symposium on Code Generation and Optimization, 2004.
11. W. Liu, J. Tuck, L. Ceze, W. Ahn, K. Strauss, J. Renau, and J. Torrellas. POSH: a TLS compiler that exploits program structure. In PPoPP'06: Proceedings of the 11th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2006.
12. K. Manassiev, M. Mihailescu, and C. Amza. Exploiting distributed version concurrency in a transactional memory cluster. In PPoPP'06: Proceedings of the eleventh ACM SIGPLAN symposium on Principles and practice of parallel programming, 2006.
13. M. Mehrara, J. Hao, P.-C. Hsu, and S. Mahlke. Parallelizing sequential applications on commodity hardware using a low-cost software transactional memory. In Proceedings of the 2009 ACM SIGPLAN Conference on Programming Language Design and Implementation, 2009.
14. C. E. Oancea and A. Mycroft. Software thread-level speculation: an optimistic library implementation. In IWMSE'08: Proceedings of the 1st International Workshop on Multicore Software Engineering, 2008.
15. L.-N. Pouchet. PolyBench: The Polyhedral Benchmark suite. http://www-roc.inria.fr/-pouchet/software/polybench.
16. C. G. Quiñones, C. Madriles, J. Sánchez, P. Marcuello, A. González, and D. M. Tullsen. Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. In Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation, 2005.
17. A. Raman, H. Kim, T. R. Mason, T. B. Jablin, and D. I. August. Speculative parallelization using software multi-threaded transactions. In Proceedings of the 15th International Conference on Architectural Support for Programming Languages and Operating Systems, 2010.
18. S. Rus, L. Rauchwerger, and J. Hoef inger. Hybrid analysis: static & dynamic memory reference analysis. Int. J. Parallel Program., 31:251-283, August 2003.
19. Stanford Compiler Group. SUIF: A parallelizing and optimizing research compiler. Technical Report CSL-TR-94-620, Stanford University, Computer Systems Laboratory, 1994.
20. J. G. Steffan, C. Colohan, A. Zhai, and T. C. Mowry. The STAMPede approach to thread-level speculation. ACM Transactions on Computer Systems, 23(3):253-300, February 2005.
21. J. G. Steffan, C. B. Colohan, A. Zhai, and T. C. Mowry. A scalable approach to thread-level speculation. In Proceedings of the 27th International Symposium on Computer Architecture, 2000.
22. C. Tian, M. Feng, V. Nagarajan, and R. Gupta. Copy or discard execution model for speculative parallelization on multicores. In MICRO'08: Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture, 2008.
23. R. M. Yoo and H.-H. S. Lee. Helper transactions: Enabling thread-level speculation via a transactional memory system. In PESPMA'08: Workshop on Parallel Execution of Sequential Programs on Multi-core Architectures, 2008.
24. Y. Zhang, L. Rauchwerger, and J. Torrellas. Hardware for speculative parallelization of partially-parallel loops in DSM multiprocessors. In The 5TH International Symposium on High-Performance Computer Architecture, 1999.
25. H. Zhong, M. Mehrara, S. Lieberman, and S. Mahlke. Uncovering hidden loop level parallelism in sequential applications. In HPCA'08: Proceedings of the 14th International Symposium on High-Performance Computer Architecture, 2008.