An adaptive write buffer management scheme for flash-based ssds

ACM Transactions on Storage

Volumn 8, Issue 1, 2012, Pages

  Wu, Guanying ^a   He, Xubin ^a   Eckart, Ben ^b  

^a VIRGINIA COMMONWEALTH UNIVERSITY   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

Flash aware cache; NAND flash memory; SSD; Write buffer

Indexed keywords

BUFFER MANAGEMENT; CACHE ALGORITHMS; CACHE SCHEME; DISK I/O; FLASH-AWARE CACHE; HARD DISK DRIVE; LOWER-POWER CONSUMPTION; NAND FLASH; NAND FLASH MEMORY; PHYSICAL CHARACTERISTICS; REPLACEMENT POLICY; SOLID STATE DRIVES; SPACE MANAGEMENT; SPATIAL LOCALITY; SSD; TEMPORAL LOCALITY; TIME-PERIODS; TRACE DRIVEN SIMULATION; WRITE BUFFER;

DATA STORAGE EQUIPMENT; HARDWARE;

HARD DISK STORAGE;

EID: 84863393336     PISSN: 15533077     EISSN: 15533093     Source Type: Journal    
DOI: 10.1145/2093139.2093140     Document Type: Article

References (61)

1. AGRAWAL, N., PRABHAKARAN, V.,WOBBER, T.,DAVIS, J. D.,MANASSE, M., AND PANIGRAHY, R. 2008. Design tradeoffs for SSD performance. In Proceedings of the USENIX 2008 Annual Technical Conference on Annual Technical Conference.
2. BALAKRISHNAN, M., KADAV, A., PRABHAKARAN, V., AND MALKHI, D. 2010. Differential RAID: Rethinking RAID for SSD reliability. ACM Trans. Storage 6, 2, 1-22.
3. BANSAL, S. ANDMODHA, D. S. 2004. CAR: Clock with Adaptive Replacement. In Proceedings of the 3rd USENIX Conference on File and Storage Technologies (FAST'04). 187-200.
4. BEZ, R., CAMERLENGHI, E., MODELLI, A., AND VISCONTI, A. 2003. Introduction to flash memory. Proc. IEEE 91, 489-502.
5. CHANG, Y., LIN, J.,HSIEH, J., AND KUO, T. 2010. A strategy to emulate NOR flash with NAND flash. ACMTrans. .Storage 6, 2, 1-23.
6. CHANG, Y.-H., HSIEH, J.-W., AND KUO, T.-W. 2007. Endurance enhancement of flash-memory storage systems: An efficient static wear leveling design. In Proceedings of the IEEE/ACMDesign Automation Conference (DAC).
7. CHEN, F., LEE, R., AND ZHANG, X. 2011. Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA). IEEE.
8. EETIMES. 2010. http://www.eetimes.com/electronics-news/4207194/Toshiba rolls 24 nm NAND flash. .ENGADET. http://www.engadget.com/2010/04/19/.
9. GILL, B. S. ANDMODHA, D. S. 2005. WOW:Wise Ordering ForWrites-Combining spatial and temporal locality in non-volatile caches. In Proceedings of the 4th Conference on USENIX Conference on File and Storage Technologies (FAST'05). USENIX Association, Berkeley, CA.
10. GUPTA, A., KIM, Y., AND URGAONKAR, B. 2009. DFTL: A flash translation layer employing demand-based selective caching of page-level address mappings. In Proceedings of the 14th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS'09). ACM, New York, 229-240.
11. GUPTA, A., PISOLKAR, R.,URGAONKAR, B., AND SIVASUBRAMANIAM, A. 2011. Leveraging value locality in optimizing NANDflash-based SSDs. In Proceedings of the 9th USENIX Conference on File and Stroage Technologies. .USENIX Association.
12. HAT, R. 2010. The journalling flash file system, version 2. .http://sourceware.org/jffs2/
13. HEWLETT-PACKARD LABORATORIES. cello99 traces. http://tesla.hpl.hp.com/ opensource/.
14. HU, J., JIANG, H., TIAN, L., AND XU, L. 2010. PUD-LRU: An erase-efficient write buffer management algorithm for flash memory SSD. In Proceedings of the International Symposium on Modeling, Analysis, and Simulation of Computer Systems. 69-78.
15. HUTSELL, W., BOWEN, J., AND EKKER, N. 2008. Flash solid-state disk reliability. Tech. rep.
16. INTEL. 2009. Intel X25-M SATA Solid State Drive. http://download.intel. com/design/flash/nand/mainstream/322296.pdf.
17. INTEL. 2010. http://www.intel.com/pressroom/archive/releases/ 20100201comp.htm.
18. JIANG, S., DING, X., CHEN, F., TAN, E., AND ZHANG, X. 2005. DULO: An effective buffer cache management scheme to exploit both temporal and spatial locality. In Proceedings of the 4th Conference on USENIX Conference on File and Storage Technologies (FAST'05). USENIX Association, Berkeley, CA.
19. JIANG, S. AND ZHANG, X. 2002. LIRS: An efficient low inter-reference recency set replacement policy to improve buffer cache performance. In Proceedings of the ACM SIGMATRICS International Conference Measurement and Modeling of Computer Systems, 31-42. (Pubitemid 35009507)
20. JO, H., KANG, J.-U., PARK, S.-Y., KIM, J.-S., AND LEE, J. 2006. FAB: Flash-Aware Buffer management policy for portable media players. IEEE Trans. Consum. Elect. 52, 2, 485-493. (Pubitemid 44203122)
21. JOHNSON, T. AND SHASHA, D. 1994. 2Q: A low overhead high performance buffer management replacement algorithm. In Proceedings of the 20th International Conference on Very Large Data Bases (VLDB'94). .Morgan Kaufmann Publishers Inc., San Francisco, CA, 439-450.
22. JOSEPHSON, W., BONGO, L., LI, K., AND FLYNN, D. 2010. DFS: A file system for virtualized flash storage. ACM Trans. Storage 6, 3, 1-25.
23. JUNG, J., WON, Y., KIM, E., SHIN, H., AND JEON, B. 2010. FRASH: Exploiting storage class memory in hybrid file system for hierarchical storage. ACM Trans. Storage 6, 1, 1-25.
24. KANG, J. U., JO, H., KIM, J. S., AND LEE, J. 2006. A superblock-based flash translation layer for nand flash memory. In Proceedings of the International Conference on Embedded Software.
25. KANG, S., PARK, S., JUNG, H., SHIM, H., AND CHA, J. 2009. Performance trade-offs in using NVRAM write buffer for flash memory-based storage devices. IEEE Trans. Comput. 58, 6, 744-758.
26. KAREDLA, R., LOVE, J. S., AND WHERRY, B. G. 1994. Caching strategies to improve disk system performance. .IEEE Comput. 27, 3, 38-46.
27. KIM, H. AND AHN, S. 2008. BPLRU: A buffermanagement scheme for improving random writes in flash storage abstract. In Proceedings of 6th USENIX Conference on File and Storage Technologies (FAST'08).
28. KIM, J. M., CHOI, J., KIM, J., NOH, S. H., MIN, S. L., CHO, Y., AND KIM, C. S. 2000. A low-overhead, highperformance unified buffer management scheme that exploits sequential and looping references. In Proceedings of the 4th Symposium on Operating System Design and Implementation (OSDI'00). 119-134.
29. KIM, J., KIM, J. M.,NOH, S.,MIN, S. L., AND CHO, Y. 2002. A space-efficient flash translation layer for compactflash systems. IEEE Trans. Consum. Electron. 48, 2, 366-375. (Pubitemid 34798899)
30. LEE, D., CHOI, J., KIM, J., NOH, S., MIN, S., CHO, Y., AND KIM, C. 2001. LRFU: A spectrum of policies that subsumes the least recently used and least frequently used policies. IEEE Trans. Comput. 50, 12, 1352-1361. (Pubitemid 34069217)
31. LEE, S.,HA, K., ZHANG, K., KIM, J., AND KIM, J. 2009. FlexFS: A flexible flash file system for MLC NAND flash memory. In Proceedings of the USENIX Annual Technical Conference. USENIX.
32. LEE, S., SHIN, D., KIM, Y.-J., AND KIM, J. 2008. LAST: Locality-aware sector translation for NAND flash memory-based storage systems. SIGOPS Oper. Syst. Rev. 42, 6, 36-42.
33. LEE, S.-W., PARK, D.-J., CHUNG, T.-S., LEE, D.-H., PARK, S.-W., AND SONG, H.-J. 2005. FAST: An FTL scheme with fully associative sector translations. In Proceedings of the UKC Conference. UKC.
34. LEE, Y.-G., JUNG, D.,KANG, D., AND KIM, J.-S. 2008. uFTL: Amemory-efficient flash translation layer supporting multiple mapping granularities. In Proceedings of the 8th ACM International Conference on Embedded Software (EMSOFT'08). ACM, New York, 21-30.
35. MANNING, C. 2010. Yet another flash file system. http://www.yaffs.net/.
36. MASON, L. 2009. Rethinking SSDs. http://www.denali.com/wordpress/index. php/dmr/2009/07/23/rethinkingssds.
37. MEGIDDO, N. AND MODHA, D. 2003. ARC: A self-tuning, low overhead replacement cache. In Proceedings of the 2nd USENIX Conference on File and Storage Technologies (FAST'03). 115-130.
38. MEGIDDO, N. AND MODHA, D. S. 2004. Outperforming LRU with an adaptive replacement cache algorithm. .Computer 37, 4, 58-65.
39. NEWEGG. 2009a. Intel X25-M Mainstream SSDSA2MH160G2C1 2.5-inch160GB SATA II MLC Internal Solid state disk (SSD). http://www.newegg.com/Product/Product. aspx?Item=N82E16820167017.
40. NEWEGG. 2009b. Western Digital VelociRaptor WD3000HLFS 300GB 10000 RPM 16MB cache SATA 3.0Gb/s 3.5-inch internal hard drive-OEM. http://www.newegg.com/ Product/Product.aspx?Item= N82E16822136322.
41. NICOLA, V., DAN, A., AND DIAS, D. 1992. Analysis of the generalized clock buffer replacement scheme for database transaction processing. In Proceedings of the ACM SIGMETRICS Joint International Conference on Measurement and Modeling of Computer Systems. ACM, 35-46.
42. O'NEIL, E. J., O'NEIL, P. E., AND WEIKUM, G. 1993. The LRU-K page replacement algorithm for database disk buffering. In Proceedings of the ACM SIGMOD International Conference on Management of Data (SIGMOD'93). ACM, New York, 297-306.
43. ONFI. 2010. http://onfi.org/.
44. PARK, S.-Y., JUNG, D., KANG, J.-U., KIM, J.-S., AND LEE, J. 2006. CFLRU: A replacement algorithm for flash memory. In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES'06). ACM, New York, 234-241. (Pubitemid 47113111)
45. REN, J. AND YANG, Q. 2011. I-CASH: Intelligently Coupled Array of SSD and HDD. In Proceedings of the 17th IEEE International Symposium on High Performance Computer Architecture (HPCA).
46. ROSENBLUM, M. AND OUSTERHOUT, J. K. 1992. The design and implementation of a log-structured file system. .ACM Trans. Comput. Syst. 10, 1, 26-52. (Pubitemid 23598979)
47. SAMSUNG. 2010. http://www.samsung.com/global/business/semiconductor/ products/fusionmemory/Products-OneNAND.html.
48. SHIM, H., SEO, B.-K., KIM, J.-S., AND MAENG, S. 2010. An adaptive partitioning scheme for DRAM-based cache in solid state drives. In Proceedings of the 26th IEEE Symposium on Mass Storage Systems and Technologies (MSST). 1-12.
49. SHIMPI, A. L. 2009. Intel x25-m g2: Dissected and performance preview. http://www.anandtech.com/storage/showdoc.aspx?i=3607.
50. SILICONSYSTEMS. 2005. Increasing flash solid state disk reliability. Tech. rep.
51. SIMPLESCALAR LLC. 2009. The simplescalar tool set. http://www. simplescalar.com/.
52. SOUNDARARAJAN, G., PRABHAKARAN, V., BALAKRISHNAN, M., AND WOBBER, T. 2010. Extending SSD lifetimes with disk-based write caches. In Proceedings of the 8th USENIX Conference on File and Storage Technologies (FAST'10). USENIX.
53. STORAGE PERFORMANCE COUNCIL. 2010. SPC trace file format specification. http://traces.cs.umass.edu/index. .php/Storage/Storage.
54. SUN, G., JOO, Y., CHEN, Y., NIU, D., XIE, Y., CHEN, Y., AND LI, H. 2010. A hybrid solid-state storage architecture for the performance, energy consumption, and lifetime improvement. In Proceedings of the 16th IEEE International Symposium on High-Performance Computer Architecture (HPCA-16). IEEE, 141-153.
55. TOSHIBA. 2010. http://www.toshiba.com/taec/news/press-releases/2006/memy- 06-337.jsp.
56. UMASS. 2007. Umass trace repository. http://traces.cs.umass.edu/index. php/Storage/Storage.
57. WANG, Y., SHU, J., ZHANG, G., XUE, W., AND ZHENG, W. 2010. SOPA: Selecting the optimal caching policy adaptively. ACM Trans. Storage 6, 2, 1-18.
58. WESTERN DIGITAL. December 2008. WD VelociRaptor SATA hard drives. http://www.wdc.com/en/library/sata/2879-701282.pdf.
59. WU, C.-H. AND KUO, T.-W. 2006. An adaptive two-level management for the flash translation layer in embedded systems. In Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD'06). ACM, New York, 601-606.
60. ZHOU, Y., CHEN, Z., AND LI, K. 2004. Second-level buffer cache management. IEEE Trans. Parallel Distrib. .Syst. 15, 6, 505-519.
61. ZHOU, Y., PHILBIN, J., AND LI, K. 2001. The multi-queue replacement algorithm for second level buffer caches. .In Proceedings of the USENIX Annual Technical Conference (General Track). USENIX Association, Berkeley, CA, 91-104.