A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

2011 Proceedings of Technical Papers: IEEE Asian Solid-State Circuits Conference 2011, A-SSCC 2011

Volumn , Issue , 2011, Pages 233-236

  Chan, Chi Hang ^a   Zhu, Yan ^a   Chio, U Fat ^a   Sin, Sai Weng ^a   Seng Pan, U ^a   Martins, R P ^a,b  

^a State Key Laboratory of Analog and Mixed Signal VLSI   (Macao)

^b INSTITUTO SUPERIOR TÉCNICO   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

90NM CMOS; ANALOG TO DIGITAL CONVERTERS; DRIVING CAPABILITY; DYNAMIC COMPARATORS; HIGH RESOLUTION; LOW NOISE; LOW OFFSET; OFFSET CALIBRATION; OFFSET VOLTAGE; RE-CONFIGURABLE; SPEED DYNAMICS;

CALIBRATION; COMPARATORS (OPTICAL); DIGITAL CIRCUITS;

ANALOG TO DIGITAL CONVERSION;

EID: 84863053133     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASSCC.2011.6123645     Document Type: Conference Paper

References (5)

1. G. Van der Plas, S. Decoutere, and S. Donnay, "A0.19pJ/Conversion- step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process," in IEEE ISSCC Dig. Tech. Papers, pp. 556-567, Sep. 2008.
2. Masaya Miyahara, Yusuke Asada, Daehwa Paik and Akira Matsuzawa, "A Low-Noise Self-Calibrating Dynamic Comparator for High-Speed ADCs," in IEEE A-SSCC, pp. 269-272, Nov. 2008.
3. Bernhard Goll and Horst Zimmermann,"A Clocked, Regenerative Comparator in 0.12μm CMOS with Tunable Sensitivity," in IEEE ESSCIRC, pp.408-411, Sep. 2007.
4. Pierluigi Nuzzo, Fernando De Bernardinis, Pierangelo Terreni, and Geert Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," IEEE Trans. Circuits Syst. I, vol. 55, no. 6, pp. 1441-1454, July. 2008.
5. Mohamed Abbas, Yasuo Furukawa, Satoshi Komatsu, Takahiro J. Yamaguchi, and Kunihiro Asada, "Clocked Comparator for High-Speed Applications in 65nm Technology" in IEEE A-SSCC, pp. 1-4, Nov. 2010