Scaling feasibility study of planar thin floating gate (FG) NAND flash devices and size effect challenges beyond 20nm

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2011, Pages

  Lue, Hang Ting ^a   Hsiao, Yi Hsuan ^a   Hsieh, Kuang Yeu ^a   Wang, Szu Yu ^b   Yang, Tahone ^b   Chen, Kuang Chao ^b   Lu, Chih Yuan ^a  

^a MACRONIX INTERNATIONAL CO LTD   (Taiwan)

^b Technology Development Center   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

CHANNEL DEVICE; CONTROL GATES; DEVICE PARAMETERS; FEASIBILITY STUDIES; FLOATING GATES; FRINGING FIELDS; MEMORY WINDOW; NAND FLASH; SIZE EFFECTS; SUBTHRESHOLD SLOPE; TCAD SIMULATION;

DEGRADATION; ELECTRON DEVICES; THREE DIMENSIONAL COMPUTER GRAPHICS;

EQUIPMENT;

EID: 84863049778     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2011.6131519     Document Type: Conference Paper

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