Combining module selection and replication for throughput-driven streaming programs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2012, Pages 1018-1023

  Cong, Jason ^a   Huang, Muhuan ^a   Liu, Bin ^a   Zhang, Peng ^a   Zou, Yi ^a  

^a University of California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FIELD PROGRAMMABLE GATE ARRAYS (FPGA); HIGH LEVEL SYNTHESIS; INTEGRATED CIRCUIT DESIGN;

DATA PARALLELISM; DATA-INTENSIVE APPLICATION; DESIGN SPACE EXPLORATION; MODULE SELECTION; MPEG-4 DECODERS; STREAMING APPLICATIONS; STREAMING PROCESSING; THROUGHPUT CONSTRAINTS;

MOTION PICTURE EXPERTS GROUP STANDARDS;

EID: 84862082123     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/date.2012.6176645     Document Type: Conference Paper

References (22)

1. M. I. Gordon, W. Thies, and S. Amarasinghe, "Exploiting coarse-grained task, data, and pipeline parallelism in stream programs," SIGOPS, vol. 40, pp. 151-162, 2006.
2. M. I. Gordon et al., "A stream compiler for communication-exposed architectures," SIGARCH, vol. 30, pp. 291-303, 2002.
3. M. Kudlur and S. Mahlke, "Orchestrating the execution of stream programs on multicore platforms," SIGPLAN, vol. 43, pp. 114-124, 2008.
4. A. Hormati et al., "MacroSS: macro-SIMDization of streaming applications,"SIGARCH, vol. 38, pp. 285-296, 2010.
5. A. Hormati et al., "Flextream: Adaptive compilation of streaming applications for heterogeneous architectures," in PACT, 2009, pp. 214-223.
6. S. Liao et al., "Data and computation transformations for Brook streaming applications on multiprocessors," in CGO, 2006, pp. 196-207.
7. A. Udupa, R. Govindarajan, and M. J. Thazhuthaveetil, "Synergistic execution of stream programs on multicores with accelerators," SIGPLAN, vol. 44, pp. 99-108, 2009.
8. A. Hagiescu et al., "A computing origami: Folding streams in FPGAs,"in DAC, 2009, pp. 282-287.
9. F. Plavec, Z. Vranesic, and S. Brown, "Enhancements to FPGA design methodology using streaming," in FPL 2009, 2009, pp. 294-301.
10. M. Ishikawa and G. De Micheli, "A module selection algorithm for high-level synthesis," in ISCAS, 1991, pp. 1777-1780 vol.3.
11. I. Ahmad, M. Dhodhi, and C. Chen, "Integrated scheduling, allocation and module selection for design-space exploration in high-level synthesis,"CDT, vol. 142, no. 1, pp. 65-71, 1995.
12. K. Ito, L. Lucke, and K. Parhi, "ILP-based cost-optimal DSP synthesis with module selection and data format conversion," VLSI, vol. 6, no. 4, pp. 582-594, 1998.
13. W. Sun, M. J. Wirthlin, and S. Neuendorffer, "FPGA pipeline synthesis design exploration using module selection and resource sharing," TCAD, vol. 26, no. 2, pp. 254-265, 2007.
14. D. Chen, J. Cong, and J. Xu, "Optimal module and voltage assignment for low-power," in ASP-DAC, 2005, pp. 850-855.
15. W. Thies and S. Amarasinghe, "An empirical characterization of stream programs and its implications for language and compiler design," in PACT, 2010, pp. 365-376.
16. E. Lee and D. Messerschmitt, "Synchronous data flow," Proceedings of the IEEE, vol. 75, no. 9, pp. 1235-1245, 1987.
17. "StreamIt benchmarks," http://groups.csail.mit.edu/cag/ streamit/shtml/benchmarks.shtml.
18. E. A. Lee and D. G. Messerschmitt, "Static scheduling of synchronous data flow programs for digital signal processing," Computers, IEEE Transactions on, vol. C-36, no. 1, pp. 24-35, 1987.
19. Govindarajan et al., "Rate-optimal schedule for multi-rate DSP computations,"J. VLSI Signal Process. Syst., vol. 9, pp. 211-232, 1995.
20. J. Cong et al., "High-level synthesis for fpgas: From prototyping to deployment," TCAD, vol. 30, no. 4, pp. 473-491, 2011.
21. P. Schumacher et al., "A scalable, multi-stream mpeg-4 video decoder for conferencing and surveillance applications," in ICIP 2005, vol. 2, 2005, pp. II-886-9.
22. "GNU Linear Programming Kit," http://www.gnu.org/software/glpk.