Performance analysis of thread mappings with a holistic view of the hardware resources

ISPASS 2012 - IEEE International Symposium on Performance Analysis of Systems and Software

Volumn , Issue , 2012, Pages 156-167

  Wang, Wei ^a   Dey, Tanima ^a   Mars, Jason ^a   Tang, Lingjia ^a   Davidson, Jack W ^a   Soffa, Mary Lou ^a  

^a University of Virginia   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BRANCH PREDICTORS; CHIP MULTIPROCESSOR; CRITICAL ISSUES; HARDWARE RESOURCES; HOLISTIC VIEW; IN-DEPTH ANALYSIS; L2 CACHE; LINUX SCHEDULERS; MAPPING ALGORITHMS; MEMORY DISAMBIGUATION; MEMORY RESOURCES; MULTIPLE RESOURCES; OFF-CHIP MEMORIES; PERFORMANCE ANALYSIS; PERFORMANCE IMPACT; PERFORMANCE IMPROVEMENTS; PROCESSOR RESOURCES; RESOURCE MANAGEMENT; SHARED RESOURCES;

COMPUTER OPERATING SYSTEMS; CONFORMAL MAPPING; HARDWARE; MULTIPROCESSING SYSTEMS;

CACHE MEMORY;

EID: 84862074462     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISPASS.2012.6189222     Document Type: Conference Paper

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