Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 1, Issue , 2005, Pages 459-464

  Lai, Xiaolue ^a   Wan, Yayun ^a   Roychowdhury, Jaijeet ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; COMPUTER AIDED DESIGN; EQUIVALENT CIRCUITS; JITTER; LOCKS (FASTENERS); OSCILLISTORS; SPICE; VARIABLE FREQUENCY OSCILLATORS;

ACCURATE PREDICTION; LC VOLTAGECONTROLLED OSCILLATOR (VCO); NONLINEAR TECHNIQUES; ORDERS OF MAGNITUDE; PHASELOCKED LOOP (PLLS); QUALITATIVE FEATURES; SEMICONDUCTOR DESIGN; SIMULATION TECHNIQUE;

PHASE LOCKED LOOPS;

EID: 84861451048     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120913     Document Type: Conference Paper

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