HORNET: A cycle-level multicore simulator

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 31, Issue 6, 2012, Pages 890-903

  Ren, Pengju ^a   Lis, Mieszko ^b   Cho, Myong Hyon ^b   Shim, Keun Sup ^b   Fletcher, Christopher W ^b   Khan, Omer ^c   Zheng, Nanning ^a   Devadas, Srinivas ^b  

^a XI'AN JIAOTONG UNIVERSITY   (China)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c UNIVERSITY OF CONNECTICUT   (United States)

Author keywords

Multicore simulation; network on chip; parallel simulation

Indexed keywords

ADAPTIVE ROUTING; CYCLE ACCURATE; DIMENSION-ORDERED ROUTING; DRIVING POWER; HARDWARE PARAMETERS; HYPER-THREADING; INTERCONNECT GEOMETRY; MEMORY HIERARCHY; MULTI CORE; NETWORK ON CHIP; NETWORK-ON-CHIP ARCHITECTURES; NOC DESIGN; OPEN-SOURCE; PARALLEL SIMULATIONS; PHYSICAL CORE; VIRTUAL CHANNELS;

COMPUTER ARCHITECTURE; COMPUTER SIMULATION; SERVERS; VLSI CIRCUITS;

ROUTERS;

EID: 84861449365     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2012.2184760     Document Type: Article

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