A reversible processor architecture and its reversible logic design

Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

Volumn 7165 LNCS, Issue , 2012, Pages 30-42

  Thomsen, Michael Kirkedal ^a   Axelsen, Holger Bock ^a   Glück, Robert ^a  

^a UNIVERSITY OF COPENHAGEN   (Denmark)

Author keywords

[No Author keywords available]

Indexed keywords

INSTRUCTION SET; PROCESSOR ARCHITECTURES; REVERSIBLE COMPUTING; REVERSIBLE CONTROL; REVERSIBLE LOGIC;

LOGIC DESIGN;

COMPUTER ARCHITECTURE;

EID: 84860818514     PISSN: 03029743     EISSN: 16113349     Source Type: Book Series    
DOI: 10.1007/978-3-642-29517-1_3     Document Type: Conference Paper

References (28)

1. Axelsen, H.B.: Clean Translation of an Imperative Reversible Programming Language. In: Knoop, J. (ed.) CC 2011. LNCS, vol. 6601, pp. 144-163. Springer, Heidelberg (2011)
2. Axelsen, H.B., Glück, R.: A Simple and EfficientUniversal Reversible Turing Machine. In: Dediu, A.-H., Inenaga, S., Martín-Vide, C. (eds.) LATA 2011. LNCS, vol. 6638, pp. 117-128. Springer, Heidelberg (2011)
3. Axelsen, H.B., Glück, R.: WhatDo Reversible Programs Computě In: Hofmann, M. (ed.) FOSSACS 2011. LNCS, vol. 6604, pp. 42-56. Springer, Heidelberg (2011)
4. Axelsen, H.B., Glück, R., Yokoyama, T.: Reversible Machine Code and Its AbstractProcessor Architecture. In: Diekert, V., Volkov, M.V., Voronkov, A. (eds.) CSR 2007. LNCS, vol. 4649, pp. 56-69. Springer, Heidelberg (2007)
5. Barenco, A., Bennett, C.H., Cleve, R., DiVincenzo, D.P., Margolus, N., Shor, P., Sleator, T., Smolin, J.A., Weinfurter, H.: Elementary gates for quantum computation. Physical Review A 52(5), 3457-3467 (1995)
6. Burignat, S., Thomsen, M.K., Klimczak, M., Olczak, M., De Vos, A.: Interfacing Reversible Pass-Transistor CMOS Chips with Conventional Restoring CMOS Circuits. In: De Vos, A., Wille, R. (eds.) RC 2011. LNCS, vol. 7156, pp. 113-123. Springer, Heidelberg (2012)
7. Cezzar, R.: The design of a processor architecture capable of forward and reverse execution. In: IEEE Proceedings of the SOUTHEASTCON 1991, vol. 2, pp. 885-890. IEEE (1991)
8. Cuccaro, S.A., Draper, T.G., Kutin, S.A., Moulton, D.P.: A new quantum ripplecarry addition circuit. arXiv:quant-ph/0410184v1 (2005)
9. De Vos, A.: Reversible Computing: Fundamentals, Quantum Computing and Applications. Wiley-VCH (2010)
10. De Vos, A., Burignat, S., Thomsen, M.K.: Reversible implementation of a discrete integer linear transformation. Journal of Multiple-Valued Logic and SoftComputing 18(1), 25-35 (2012)
11. Feynman, R.P.: Feynman Lectures on Computation. Addison-Wesley (1996)
12. Frank, M.P.: Reversibility for EfficientComputing. Ph.D. thesis, EECS Department, Massachusetts Institute of Technology (1999)
13. Fredkin, E., Toffoli, T.: Conservative logic. International Journal of Theoretical Physics 21(3-4), 219-253 (1982)
14. Landauer, R.: Irreversibility and heatgeneration in the computing process. IBM Journal of Research and Development5(3), 183-191 (1961)
15. Lutz, C.: Janus: A time-reversible language. A letter to R. Landauer (1986), http://www.tetsuo.jp/ref/janus.html
16. Maslov, D., Dueck, G., Miller, D.: Synthesis of Fredkin-Toffoli reversible networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13(6), 765-769 (2005)
17. Morita, K.: A Simple Universal Logic Elementand Cellular Automata for Reversible Computing. In: Margenstern, M., Rogozhin, Y. (eds.) MCU 2001. LNCS, vol. 2055, pp. 102-113. Springer, Heidelberg (2001)
18. Patterson, D.A., Hennessy, J.L.: Computer Organization & Design: the hardware/software interface, 2nd edn. Morgan Kaufmann Publishers (1997)
19. Shende, V., Bullock, S., Markov, I.: Synthesis of quantum-logic circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 25(6), 1000-1010 (2006)
20. Thomsen, M.K., Axelsen, H.B.: Parallelization of reversible ripple-carry adders. Parallel Processing Letters 19(1), 205-222 (2009)
21. Thomsen, M.K., Glück, R., Axelsen, H.B.: Reversible arithmetic logic unitfor quantum arithmetic. Journal of Physics A: Mathematical and Theoretical 43(38), 382002 (2010)
22. Van Rentergem, Y., De Vos, A.: Optimal design of a reversible full adder. International Journal of Unconventional Computing 1(4), 339-355 (2005)
23. Vedral, V., Barenco, A., Ekert, A.: Quantum networks for elementary arithmetic operations. Physical Review A 54(1), 147-153 (1996)
24. Vieri, C.J.: Reversible Computer Engineering and Architecture. Ph.D. thesis, EECS Department, Massachusetts Institute of Technology (1999)
25. Wille, R., Drechsler, R.: Towards a Design Flow for Reversible Logic. Springer Science (2010)
26. Wille, R., Offermann, S., Drechsler, R.: SyReC: A programming language for synthesis of reversible circuits. In: Proceedings of the Forum on Specification & Design Languages, pp. 1-6. IET, Southhampton (2010)
27. Yokoyama, T., Axelsen, H.B., Glück, R.: Principles of a reversible programming language. In: Proceedings of Computing Frontiers, pp. 43-54. ACM (2008)
28. Yokoyama, T., Glück, R.: A reversible programming language and its invertible self-interpreter. In: Proceedings of Partial Evaluation and Program Manipulation, pp. 144-153. ACM (2007)