Bubble Razor: An architecture-independent approach to timing-error detection and correction

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 55, Issue , 2012, Pages 488-489

  Fojtik, Matthew ^a   Fick, David ^a   Kim, Yejoong ^a   Pinckney, Nathaniel ^a   Harris, David ^b   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

^b HARVEY MUDD COLLEGE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CORRECT ERROR; DELAY ERRORS; ERROR-DETECTION TECHNIQUES; HOLD TIME; INVASIVENESS; LOW-VOLTAGE; MINIMUM DELAY; TIMING MARGIN; TIMING VARIATIONS;

ERRORS;

EID: 84860700885     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2012.6177103     Document Type: Conference Paper

References (6)

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3. D. Blaauw, et al., "RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance," ISSCC Dig. Tech. Papers, pp. 400-401, 2008.
4. K. Bowman, et al., "Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance," ISSCC Dig. Tech Papers, pp. 402-403, 2008.
5. D. Ernst, et al., "Razor: a low-power pipeline based on circuit-level timing speculation," IEEE International Symp. on Microarchitecture, pp. 7-18, 2003.
6. G. Karypis, et al., "Multilevel hypergraph partitioning: applications in VLSI domain," IEEE Design Automation Conf., pp. 526-529, 1997.