Design, integration and implementation of the DySER hardware accelerator into OpenSPARC

Proceedings - International Symposium on High-Performance Computer Architecture

Volumn , Issue , 2012, Pages 115-126

  Benson, Jesse ^a   Cofell, Ryan ^a   Frericks, Chris ^a   Ho, Chen Han ^a   Govindaraju, Venkatraman ^a   Nowatzki, Tony ^a   Sankaralingam, Karthikeyan ^a  

^a UNIVERSITY OF WISCONSIN MADISON   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATOR DESIGN; DESIGN POINTS; HARDWARE ACCELERATORS; MICROBENCHMARKS; NON-INTRUSIVE; PHYSICAL DESIGN; PROCESSOR PERFORMANCE; QUANTITATIVE RESULT;

COMPUTER ARCHITECTURE; COMPUTER OPERATING SYSTEMS; DESIGN; MICROPROCESSOR CHIPS; SUPERCOMPUTERS;

PROGRAM COMPILERS;

EID: 84860350225     PISSN: 15300897     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/HPCA.2012.6168949     Document Type: Conference Paper

References (19)

1. Impact compiler. http://impact.crhc.illinois.edu/.
2. M. Baron. Cortex-A8: High speed, low power. Microprocessor Report, 2005.
3. J. Benson, R. Cofell, C. Frericks, C.-H. Ho, V. Govindaraju, T. Nowatzki, and K. Sankaralingam. OpenSPLySER: The Integrated OpenSPARC and DySER design. Technical report, Department of Computer Sciences, The University of Wisconsin-Madison, Madison, WI, 2012.
4. T. J. Callahan, J. R. Hauser, and J.Wawrzynek. The garp architecture and c compiler. Computer, 33:62-69, April 2000.
5. N. K. Choudhary, S. V. Wadhavkar, T. A. Shah, H. Mayukh, J. Gandhi, B. H. Dwiel, S. Navada, H. H. Najaf-abadi, and E. Rotenberg. Fabscalar: Composing synthesizable rtl designs of arbitrary cores within a canonical superscalar template. In ISCA '11.
6. M. Fillo, S. W. Keckler, W. J. Dally, N. P. Carter, A. Chang, Y. Gurevich, andW. S. Lee. The m-machine multicomputer. In MICRO '95.
7. V. Govindaraju, C.-H. Ho, and K. Sankaralingam. Dynamically specialized datapaths for energy efficient computing. In HPCA-17, 2011.
8. S. Gupta, S. Feng, A. Ansari, S. Mahlke, and D. August. Bundled execution of recurring traces for energy-efficient general purpose processing. In MICRO 2011.
9. R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B. C. Lee, S. Richardson, C. Kozyrakis, and M. Horowitz. Understanding sources of inefficiency in general-purpose chips. In ISCA '10.
10. M. Hempstead, G.-Y. Wei, and D. Brooks. Navigo: An early-stage model to study power-constrained architectures and specialization. In Workshop on Modeling, Benchmarking, and Simulation, 2009.
11. J. H. Kelm, D. R. Johnson, M. R. Johnson, N. C. Crago, W. Tuohy, A. Mahesri, S. S. Lumetta, M. I. Frank, and S. J. Patel. Rigel: an architecture and scalable programming interface for a 1000-core accelerator. In ISCA '09.
12. C. Lattner and V. Adve. LLVM: A compilation framework for lifelong program analysis & transformation. In CGO '04, pages 75-88.
13. K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, P. Shivakumar, S.W. Keckler, and D. Burger. Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. In MICRO '06.
14. A. Smith. Explicit Data Graph Compilation, PhD Dissertation, UT-Austin, 2009.
15. A. Solomatnikov, A. Firoozshahian, O. Shacham, Z. Asgar, M.Wachs,W. Qadeer, S. Richardson, and M. Horowitz. Using a configurable processor generator for computer architecture prototyping. In MICRO '09.
16. S. Swanson, A. Putnam, M. Mercaldi, K. Michelson, A. Petersen, A. Schwerin, M. Oskin, and S. J. Eggers. Areaperformance trade-offs in tiled dataflow architectures. In ISCA '06.
17. M. B. Taylor, J. Kim, J. Miller, D. Wentzlaff, F. Ghodrat, B. Greenwald, H. Hoffman, P. Johnson, J.-W. Lee, W. Lee, A. Ma, A. Saraf, M. Seneski, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, and A. Agarwal. The raw microprocessor: A computational fabric for software circuits and general-purpose programs. IEEE Micro, 22:25-35, March 2002. (Pubitemid 34434061)
18. G. Venkatesh, J. Sampson, N. Goulding, S. Garcia, V. Bryksin, J. Lugo-Martinez, S. Swanson, and M. B. Taylor. Conservation cores: reducing the energy of mature computations. In ASPLOS '10.
19. T. Vijaykumar. Compiling for the Multiscalar Architecture, PhD Dissertation, UW-Madison, 1998.