Hardware prototyping of neural network based fetal electrocardiogram extraction

Measurement Science Review

Volumn 12, Issue 2, 2012, Pages 52-55

  Hasan, M ^a   Reaz, M ^b  

^a UNIVERSITY OF ADELAIDE   (Australia)

^b UNIVERSITI KEBANGSAAN MALAYSIA   (Malaysia)

Author keywords

Fetal electrocardiogram; FPGA; Neural network; VHDL

Indexed keywords

FECG SIGNAL; FETAL ECG; FETAL ELECTROCARDIOGRAMS; FPGA IMPLEMENTATIONS; HARDWARE PROTOTYPING; QUARTUS II; R-PEAK DETECTION; VERY HIGH SPEED INTEGRATED CIRCUITS; VHDL; VHDL-MODEL;

COMPUTER HARDWARE DESCRIPTION LANGUAGES; ELECTROCARDIOGRAPHY; HARDWARE; NEURAL NETWORKS;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

EID: 84860177207     PISSN: 13358871     EISSN: None     Source Type: Journal    
DOI: 10.2478/v10048-012-0007-8     Document Type: Article

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