Tsv redundancy: Architecture and design issues in 3-D IC

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 4, 2012, Pages 711-722

  Hsieh, Ang Chih ^a   Hwang, TingTing ^a  

^a NATIONAL TSING HUA UNIVERSITY   (Taiwan)

Author keywords

Defect tolerance; reliability; yield

Indexed keywords

3-D INTEGRATION; CRITICAL DESIGN; DEFECT TOLERANCE; DESIGN ISSUES; HIGH BANDWIDTH; HIGH DENSITY; LOW POWER; PROBABILISTIC MODELS; RECOVERY RATE; THROUGH-SILICON-VIA; VERTICAL DIRECTION; YIELD;

REDUNDANCY; RELIABILITY; THREE DIMENSIONAL;

DESIGN;

EID: 84859005993     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2107924     Document Type: Article

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