-
1
-
-
47849093494
-
Analog neural network implementation for a real-time surface classification application
-
Aug.
-
L. Gatet, H. T. Beteille, and M. Lescure, "Analog neural network implementation for a real-time surface classification application," IEEE Sensors J., vol. 8, no. 8, pp. 1413-1421, Aug. 2008.
-
(2008)
IEEE Sensors J.
, vol.8
, Issue.8
, pp. 1413-1421
-
-
Gatet, L.1
Beteille, H.T.2
Lescure, M.3
-
2
-
-
34047181683
-
A pyramidal neural network for visual pattern recognition
-
DOI 10.1109/TNN.2006.884677
-
S. L. Phung and A. Bouzerdoum, "A pyramidal neural network for visual pattern recognition," IEEE Trans. Neural Netw., vol. 18, no. 2, pp. 329-343, Mar. 2007. (Pubitemid 46522560)
-
(2007)
IEEE Transactions on Neural Networks
, vol.18
, Issue.2
, pp. 329-343
-
-
Phung, S.L.1
Bouzerdoum, A.2
-
3
-
-
33747081982
-
A fully automated recurrent neural network for unknown dynamic system identification and control
-
Jun.
-
J. S.Wang and Y. P. Chen, "A fully automated recurrent neural network for unknown dynamic system identification and control," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 6, pp. 1363-1372, Jun. 2006.
-
(2006)
IEEE Trans. Circuits Syst. I, Reg. Papers
, vol.53
, Issue.6
, pp. 1363-1372
-
-
Wang, J.S.1
Chen, Y.P.2
-
4
-
-
0031629866
-
A robust hybrid neural architecture for an industrial sensor application
-
Jun.
-
H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, "A robust hybrid neural architecture for an industrial sensor application," in Proc. IEEE Int. Symp. Circuits Syst., Jun. 1998, vol. 3, pp. 41-45.
-
(1998)
Proc. IEEE Int. Symp. Circuits Syst.
, vol.3
, pp. 41-45
-
-
Djahanshahi, H.1
Ahmadi, M.2
Jullien, G.A.3
Miller, W.C.4
-
5
-
-
0029747437
-
A modular architecture for hybrid vlsi neural networks and its application in a smart photosensor
-
Jun.
-
H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, "A modular architecture for hybrid VLSI neural networks and its application in a smart photosensor," in Proc. IEEE Int. Conf. Neural Netw., Jun. 1996, vol. 2, pp. 868-873.
-
(1996)
Proc. IEEE Int. Conf. Neural Netw.
, vol.2
, pp. 868-873
-
-
Djahanshahi, H.1
Ahmadi, M.2
Jullien, G.A.3
Miller, W.C.4
-
6
-
-
1542791539
-
Approximation of sigmoid function and the derivative for hardware implementation of artificial neurons
-
Feb.
-
K. Basterretxea, J. M. Tarela, and I. Del Campo, "Approximation of sigmoid function and the derivative for hardware implementation of artificial neurons," IEE Proc.-Circuits, Devices Syst., vol. 151, no. 1, pp. 18-24, Feb. 2004.
-
(2004)
IEE Proc.-Circuits, Devices Syst.
, vol.151
, Issue.1
, pp. 18-24
-
-
Basterretxea, K.1
Tarela, J.M.2
Del Campo, I.3
-
7
-
-
0347410661
-
Efficient digital implementation of the sigmoid function for reprogrammable logic
-
Nov.
-
M. T. Tommiska, "Efficient digital implementation of the sigmoid function for reprogrammable logic," IEE Proc. Comput. Digit. Techn., vol. 150, no. 6, pp. 403-411, Nov. 2003.
-
(2003)
IEE Proc. Comput. Digit. Techn.
, vol.150
, Issue.6
, pp. 403-411
-
-
Tommiska, M.T.1
-
8
-
-
70350148871
-
Efficient hardware implementation of the hyperbolic tangent sigmoid function
-
May
-
A. H. Namin, K. Leboeuf, R. Muscedere, H. Wu, and M. Ahmadi, "Efficient hardware implementation of the hyperbolic tangent sigmoid function," in Proc. IEEE Int. Symp. Circuits Syst., May 2009, pp. 2117-2120.
-
(2009)
Proc. IEEE Int. Symp. Circuits Syst.
, pp. 2117-2120
-
-
Namin, A.H.1
Leboeuf, K.2
Muscedere, R.3
Wu, H.4
Ahmadi, M.5
-
9
-
-
34250827744
-
Implementing neural architectures using analog vlsi circuits
-
May
-
M. A. C. Maher, S. P. Deweerth, M. A. Mahowald, and C. A. Mead, "Implementing neural architectures using analog VLSI circuits," IEEE Trans. Circuits Syst, vol. 36, no. 5, pp. 643-652, May 1989.
-
(1989)
IEEE Trans. Circuits Syst
, vol.36
, Issue.5
, pp. 643-652
-
-
Maher, M.A.C.1
Deweerth, S.P.2
Mahowald, M.A.3
Mead, C.A.4
-
10
-
-
0035721033
-
Implementation of an analog self-learning neural network
-
C. Lu, B. X. Shi, and L. Chen, "Implementation of an analog selflearning neural network," in Proc. Int. Conf. ASIC, 2001, pp. 262-265. (Pubitemid 34198385)
-
(2001)
International Conference on ASIC, Proceedings
, pp. 262-265
-
-
Lu, C.1
Shi, B.2
Chen, L.3
-
11
-
-
0027555961
-
Design and characterization of analog VLSI neural network modules
-
DOI 10.1109/4.209997
-
S. M. Gowda, B. J. Sheu, J. Choi, C. G.Hwang, and J. S. Cable, "Design and characterization of analog VLSI neural network modules," IEEE J. Solid-State Circuits, vol. 28, no. 3, pp. 301-313, Mar. 1993. (Pubitemid 23643326)
-
(1993)
IEEE Journal of Solid-State Circuits
, vol.28
, Issue.3
, pp. 301-313
-
-
Gowda Sudhir, M.1
Sheu Bing, J.2
Choi Joongho3
Hwang Chang-Gyu4
Cable James, S.5
-
12
-
-
0036579973
-
Analog VLSI neural network with digital perturbative learning
-
DOI 10.1109/TCSII.2002.802282, PII 1011092002802282
-
V. F. Koosh and R. M. Goodman, "Analog VLSI neural network with digital perturbative learning," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 49, no. 5, pp. 359-368, May 2002. (Pubitemid 34974256)
-
(2002)
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol.49
, Issue.5
, pp. 359-368
-
-
Koosh, V.F.1
Goodman, R.M.2
-
14
-
-
0026727537
-
A reconfigurable vlsi neural network
-
Jan.
-
S. Satyanarayana, Y. P. Tsividis, and H. P. Graf, "A reconfigurable VLSI neural network," IEEE J. Solid-State Circuits, vol. 27, no. 1, pp. 67-81, Jan. 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, Issue.1
, pp. 67-81
-
-
Satyanarayana, S.1
Tsividis, Y.P.2
Graf, H.P.3
-
15
-
-
0035456445
-
Quantization noise improvement in a hybrid distributed-neuron ANN architecture
-
DOI 10.1109/82.964997, PII S1057713001104167
-
H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, "Quantization noise improvement in a hybrid distributed-neuron ANN architecture," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 48, no. 9, pp. 842-846, Sep. 2001. (Pubitemid 33120706)
-
(2001)
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
, vol.48
, Issue.9
, pp. 842-846
-
-
Djahanshahi, H.1
Ahmadi, M.2
Jullien, G.A.3
Miller, W.C.4
-
16
-
-
0029717018
-
A unified synapse-neuron building block for hybrid vlsi neural networks
-
May
-
H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, "A unified synapse-neuron building block for hybrid VLSI neural networks," in Proc. IEEE Int. Symp. Circuits Syst., May 1996, vol. 3, pp. 483-486.
-
(1996)
Proc. IEEE Int. Symp. Circuits Syst.
, vol.3
, pp. 483-486
-
-
Djahanshahi, H.1
Ahmadi, M.2
Jullien, G.A.3
Miller, W.C.4
-
17
-
-
0034250277
-
Sensitivity study and improvements on a nonlinear resistive-type neuron circuit
-
Aug.
-
H. Djahanshahi, M. Ahmadi, G. A. Jullien, and W. C. Miller, "Sensitivity study and improvements on a nonlinear resistive-type neuron circuit," IEE Proc.-Circuits, Devices Syst., vol. 147, no. 4, pp. 237-242, Aug. 2000.
-
(2000)
IEE Proc.-Circuits, Devices Syst.
, vol.147
, Issue.4
, pp. 237-242
-
-
Djahanshahi, H.1
Ahmadi, M.2
Jullien, G.A.3
Miller, W.C.4
-
18
-
-
47149084750
-
Robust low-sensitivity adaline neuron based on continuous valued number system
-
Apr.
-
M. Mirhassani, M. Ahmadi, and G. A. Jullien, "Robust low-sensitivity adaline neuron based on continuous valued number system," J. Analog Integr. Circuits Signal Process., vol. 56, pp. 223-231, Apr. 2008.
-
(2008)
J. Analog Integr. Circuits Signal Process.
, vol.56
, pp. 223-231
-
-
Mirhassani, M.1
Ahmadi, M.2
Jullien, G.A.3
-
19
-
-
63049093583
-
Comparison between analog and digital neural network implementations for range-finding applications
-
Mar.
-
L. Gatet, H. T. Beteille, and F. Bony, "Comparison between analog and digital neural network implementations for range-finding applications," IEEE Trans. Neural Netw., vol. 20, no. 3, pp. 460-470, Mar. 2009.
-
(2009)
IEEE Trans. Neural Netw.
, vol.20
, Issue.3
, pp. 460-470
-
-
Gatet, L.1
Beteille, H.T.2
Bony, F.3
-
20
-
-
33750125702
-
Biologically plausible vlsi neural network implementation with asynchronous neuron and spike-based synapse
-
Aug.
-
II. S. Han, "Biologically plausible VLSI neural network implementation with asynchronous neuron and spike-based synapse," in Proc. IEEE Int. Joint Conf. Neural Netw., Aug. 2005, vol. 5, pp. 3244-3248.
-
(2005)
Proc. IEEE Int. Joint Conf. Neural Netw.
, vol.5
, pp. 3244-3248
-
-
Han II, S.1
-
21
-
-
0022737957
-
Versatile cmos linear transconductor/square-law function circuit
-
E. Seevinck and R. F. Wassenaar, "A versatile CMOS linear transconductor/ square-law function," IEEE J. Solid-State Circuits, vol. 22, no. 3, pp. 366-377, Jun. 1987. (Pubitemid 17582746)
-
(1986)
IEEE Journal of Solid-State Circuits
, vol.SC-22
, Issue.3
, pp. 366-377
-
-
Seevinck, E.1
Wassenaar Roelof, F.2
-
22
-
-
2442417897
-
Scalable closedboundary analog neural networks
-
Mar.
-
S. M. Fakhraie, H. Farshbaf, and K. C. Smith, "Scalable closedboundary analog neural networks," IEEE Trans. Neural Netw., vol. 15, no. 2, pp. 492-504, Mar. 2004.
-
(2004)
IEEE Trans. Neural Netw.
, vol.15
, Issue.2
, pp. 492-504
-
-
Fakhraie, S.M.1
Farshbaf, H.2
Smith, K.C.3
-
23
-
-
33846105772
-
An experimental study on nonlinear function computation for neural/fuzzy hardware design
-
DOI 10.1109/TNN.2006.884680
-
K. Basterretxea, J. M. Tarela, I. D. Campo, and G. Bosque, "An experimental study on nonlinear function computation for neural/fuzzy hardware design," IEEE Trans. Neural Netw., vol. 18, no. 1, pp. 266-283, Jan. 2007. (Pubitemid 46062932)
-
(2007)
IEEE Transactions on Neural Networks
, vol.18
, Issue.1
, pp. 266-283
-
-
Basterretxea, K.1
Tarela, J.M.2
Del Campo, I.3
Bosque, G.4
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