-
1
-
-
84943655909
-
Deterministic versus random testing
-
Los Angeles, CA
-
V. Agrawal and R. Mercer. Deterministic versus random testing. Int. Test Conf., Los Angeles, CA, September 1986, pp. 718–718.
-
(1986)
Int. Test Conf
, pp. 718
-
-
Agrawal, V.1
Mercer, R.2
-
2
-
-
84943649267
-
Network processor designer tackles verification nightmare
-
(Brecis Communications, Inc.), November 5
-
G. Apostol (Brecis Communications, Inc.). Network processor designer tackles verification nightmare. EE Design, November 5, 2001.
-
(2001)
EE Design
-
-
Apostol, G.1
-
3
-
-
85056978739
-
Coverage directed generation of system-level test cases for the validation of a DSP system
-
LNCS
-
L. Arditi, H. Boufaied, A. Cavanie, and V. Stehle. Coverage directed generation of system-level test cases for the validation of a DSP system. Int. Symp. on FME 2001: Formal Methods for Increasing Software Productivity, LNCS, Vol. 1, 2001.
-
Int. Symp. on FME 2001: Formal Methods for Increasing Software Productivity
, vol.1
, pp. 2001
-
-
Arditi, L.1
Boufaied, H.2
Cavanie, A.3
Stehle, V.4
-
5
-
-
84943622391
-
-
Technical Report, IBM Haifa Laboratories, Haifa, Israel
-
M. Benjamin, D. Geist, A. Hartman, G. Mas, R. Smeets, and Y. Wolfsthal. A feasibility study in formal coverage driven test generation. Technical Report, IBM Haifa Laboratories, Haifa, Israel, June 1999. http://www.haifa.il.ibm.com/projects/verification/gtcb/.
-
(1999)
A Feasibility Study in Formal Coverage Driven Test Generation
-
-
Benjamin, M.1
Geist, D.2
Hartman, A.3
Mas, G.4
Smeets, R.5
Wolfsthal, Y.6
-
6
-
-
0003272495
-
-
G. Plotkin, C. Stirling, and M. Tofte, Eds., MIT Press
-
G. Berry. The Foundations of Esterel. G. Plotkin, C. Stirling, and M. Tofte, Eds., MIT Press, 2000.
-
(2000)
The Foundations of Esterel
-
-
Berry, G.1
-
8
-
-
35148898415
-
Pavage pour une séquence de nids de boucles
-
Parallélisme et systèmes distribués
-
Y. Bouchebaba and F. Coelho. Pavage pour une séquence de nids de boucles. J. Technique et science informatiques. Parallélisme et systèmes distribués 21, numéro 5, 2002, pp. 579–603.
-
(2002)
J. Technique Et Science Informatiques
, vol.21
, Issue.5
, pp. 579-603
-
-
Bouchebaba, Y.1
Coelho, F.2
-
9
-
-
34250747282
-
Tiling and memory reuse for sequences of nested loops
-
8th Int. Euro-Par Conf. Proc. Lecture Notes in Computer Science
-
Y. Bouchebaba and F. Coelho. Tiling and memory reuse for sequences of nested loops. Euro-Par 2002, Parallel Process., 8th Int. Euro-Par Conf. Proc. Lecture Notes in Computer Science 2400, 2002, pp. 255–264.
-
(2002)
Euro-Par 2002, Parallel Process
, vol.2400
, pp. 255-264
-
-
Bouchebaba, Y.1
Coelho, F.2
-
10
-
-
85056953653
-
A new synthesizable architecture approach for verification environments applying transaction-based methodology
-
Anaheim, CA
-
R. Brackebusch, S. Muller, G.S.-Y. Sokomak, F. Grassert, and D. Timmermann. A new synthesizable architecture approach for verification environments applying transaction-based methodology. Proc. 40th Design Automation Conf. (DAC’03), Anaheim, CA, June 2003.
-
(2003)
Proc. 40Th Design Automation Conf. (DAC’03)
-
-
Brackebusch, R.1
Muller, S.2
Sokomak, G.S.3
Grassert, F.4
Timmermann, D.5
-
14
-
-
0028754935
-
Global communication and memory optimizing transformations for low power signal processing systems
-
F. Catthoor, F. Franssen, S. Wuytack, L. Nachtergaele, and H. DeMan. Global communication and memory optimizing transformations for low power signal processing systems. IEEE Workshop on VLSI Signal Process., 1994, pp. 178–187.
-
(1994)
IEEE Workshop on VLSI Signal Process
, pp. 178-187
-
-
Catthoor, F.1
Franssen, F.2
Wuytack, S.3
Nachtergaele, L.4
Deman, H.5
-
15
-
-
0003840779
-
-
(Cadence Design Systems, Inc.)(Simutech, Inc.), Kluwer Academic Publishers, Dordrecht
-
H. Chang, L. Cooke, M. Hunt, G. Martin (Cadence Design Systems, Inc.), A. McNelly and L. Todd (Simutech, Inc.). Surviving the SOC Revolution: A Guide to Platform-Based Design. Kluwer Academic Publishers, Dordrecht, 1999.
-
(1999)
Surviving the SOC Revolution: A Guide to Platform-Based Design
-
-
Chang, H.1
Cooke, L.2
Hunt, M.3
Martin, G.4
McNelly, A.5
Todd, L.6
-
16
-
-
0034821825
-
High-level architectural co-simulation using Esterel and C
-
(Motorola, Inc.)(Politecnico di Torino)
-
A. Chatelain, Y. Mathys, G. Placido (Motorola, Inc.), A. La Rosa and Luciano Lavagno (Politecnico di Torino). High-level architectural co-simulation using Esterel and C. CODES’01, pp. 189–194.
-
CODES’01
, pp. 189-194
-
-
Chatelain, A.1
Mathys, Y.2
Placido, G.3
La Rosa, A.4
Lavagno, L.5
-
17
-
-
0037688436
-
-
Intel Corporation, Revision 8, Intel Corporation, Santa Clara, CA
-
Intel Corporation, Intel IXP1200 Network Processor Family: Hardware Reference Manual, Revision 8, Intel Corporation, Santa Clara, CA, pp. 225–228, 2001.
-
(2001)
Intel IXP1200 Network Processor Family: Hardware Reference Manual
, pp. 225-228
-
-
-
18
-
-
0033722767
-
Characterizing processor architectures for programmable network interfaces
-
Santa Fe, NM, May
-
P. Crowley, M. Fiuczynski, J. Baer, and B. Bershad. Characterizing processor architectures for programmable network interfaces, Proc. 2000 Int. Conf. on Supercomputing, Santa Fe, NM, May 2000.
-
(2000)
Proc. 2000 Int. Conf. on Supercomputing
-
-
Crowley, P.1
Fiuczynski, M.2
Baer, J.3
Bershad, B.4
-
19
-
-
0033689152
-
On the complexity of loop fusion
-
A. Darte. On the complexity of loop fusion, Parallel Computing, Vol. 26, No. 9, 2000, pp. 1175–1193.
-
(2000)
Parallel Computing
, vol.26
, Issue.9
, pp. 1175-1193
-
-
Darte, A.1
-
21
-
-
0029520020
-
Structuration of the Alpha language
-
IEEE Computer Society Press, Berlin, Germany
-
F. de Dinechin, P. Quinton, and T. Risset. Structuration of the Alpha language, in Massively Parallel Programming Models, IEEE Computer Society Press, Berlin, Germany, 1995, pp. 18–24.
-
(1995)
Massively Parallel Programming Models
, pp. 18-24
-
-
De Dinechin, F.1
Quinton, P.2
Risset, T.3
-
22
-
-
0033682583
-
YAPI: Application modeling for signal processing systems
-
NY, June 5–9
-
E.A. de Kock, W.J.M. Smits, P. van der Wolf, J.-Y. Brunel, W.M. Kruijtzer, P. Lieverse, K.A. Vissers, and G. Essink. YAPI: application modeling for signal processing systems. Proc. 37th Conf. on Design Automation (DAC-00), NY, June 5–9 2000, pp. 402–405.
-
(2000)
Proc. 37Th Conf. on Design Automation (DAC-00)
, pp. 402-405
-
-
De Kock, E.A.1
Smits, W.J.M.2
Van Der Wolf, P.3
Brunel, J.-Y.4
Kruijtzer, W.M.5
Lieverse, P.6
Vissers, K.A.7
Essink, G.8
-
23
-
-
85056927748
-
Washing machine: The key to low-power
-
March 6
-
H. de Man. Washing machine: the key to low-power. EE Times, March 6, 2002, http://www.electronicstimes.com/.
-
(2002)
EE Times
-
-
De Man, H.1
-
24
-
-
0028377547
-
A strategy for array management in local memory
-
C. Eisenbeis, W. Jalby, D. Windheiser, and F. Bodin. A strategy for array management in local memory, J. Mathematical Programming: Series A, Vol. 63, No. 3, 1994, pp. 331–370.
-
(1994)
J. Mathematical Programming: Series A
, vol.63
, Issue.3
, pp. 331-370
-
-
Eisenbeis, C.1
Jalby, W.2
Windheiser, D.3
Bodin, F.4
-
25
-
-
84943648676
-
-
Technical Report, IBM Haifa Research Laboratory, Haifa, Israel
-
C. Eisner and D. Fisman. Sugar 2.0: an introduction. Technical Report, IBM Haifa Research Laboratory, Haifa, Israel, 2002.
-
(2002)
Sugar 2.0: An Introduction
-
-
Eisner, C.1
Fisman, D.2
-
27
-
-
0003880013
-
-
Addison-Wesley, Reading, MA
-
E. Gamma, R. Helm, R. Johnson, and J. Vlissides. Elements of Reusable Object-Oriented Software, Professional Computing Series, Addison-Wesley, Reading, MA, 1994.
-
(1994)
Elements of Reusable Object-Oriented Software, Professional Computing Series
-
-
Gamma, E.1
Helm, R.2
Johnson, R.3
Vlissides, J.4
-
28
-
-
0001366267
-
Strategies for cache and local memory management by global program transformation
-
D. Gannon, W. Jalby, and K. Gallivan. Strategies for cache and local memory management by global program transformation. J. Parallel and Distributed Computing, Vol. 5, No. 10, 1988, pp. 587–616.
-
(1988)
J. Parallel and Distributed Computing
, vol.5
, Issue.10
, pp. 587-616
-
-
Gannon, D.1
Jalby, W.2
Gallivan, K.3
-
29
-
-
84943600592
-
An introduction to USB development
-
J.G. Ganssle. An introduction to USB development. Embedded Systems Programming, 2002. Available at http://www.embedded.com.
-
(2002)
Embedded Systems Programming
-
-
Ganssle, J.G.1
-
30
-
-
33746947409
-
-
presented at Dagstuhl Seminar on Loop Parallelisation, Schloss Dagstuhl, Germany
-
E. de Greef, F. Catthoor, and H. de Man. Reducing storage size for static control programs mapped onto parallel architectures, presented at Dagstuhl Seminar on Loop Parallelisation, Schloss Dagstuhl, Germany, April 1996.
-
(1996)
Reducing Storage Size for Static Control Programs Mapped onto Parallel Architectures
-
-
De Greef, E.1
Catthoor, F.2
De Man, H.3
-
31
-
-
1642320614
-
Comparing analytical modeling with simulation for network processors: A case study
-
Munich, Germany
-
M. Gries, C. Kulkarni, C. Sauer, and K. Keutzer. Comparing analytical modeling with simulation for network processors: a case study, Design Automation and Test in Europe (DATE), Munich, Germany, March 2003.
-
(2003)
Design Automation and Test in Europe (DATE)
-
-
Gries, M.1
Kulkarni, C.2
Sauer, C.3
Keutzer, K.4
-
32
-
-
0026221661
-
The synchronous data-flow programming language LUSTRE
-
N. Halbwachs, P. Caspi, P. Raymond, and D. Pilaud. The synchronous data-flow programming language LUSTRE. Proc. IEEE, Vol. 79, No. 9, pp. 1305–1320, September 1991.
-
(1991)
Proc. IEEE
, vol.79
, Issue.9
, pp. 1305-1320
-
-
Halbwachs, N.1
Caspi, P.2
Raymond, P.3
Pilaud, D.4
-
33
-
-
0034986777
-
The e-language: A fresh separation of concerns
-
Zurich, Switzerland
-
Y. Hollander, M. Morley, and A. Noy. The e-language: a fresh separation of concerns. Proc. Technology of Object-Oriented Languages and Syst. (TOOLS) Europe, Zurich, Switzerland, March 1999, pp. 41–50.
-
(1999)
Proc. Technology of Object-Oriented Languages and Syst. (TOOLS) Europe
, pp. 41-50
-
-
Hollander, Y.1
Morley, M.2
Noy, A.3
-
35
-
-
84943604822
-
-
International Technology Roadmap for Semiconductors (ITRS), Technical Report, EECA, JEITA, KSIA, TSIA, SIA, and International SEMATECH
-
International Technology Roadmap for Semiconductors (ITRS). Design chapter of the 2001 edition. Technical Report, EECA, JEITA, KSIA, TSIA, SIA, and International SEMATECH, 2001. Available at http://public.itrs.net.
-
(2001)
Design Chapter of the 2001 Edition
-
-
-
38
-
-
84958772665
-
Experimental evaluation of energy behavior of iteration space tiling
-
Yorktown Heights, NY
-
M. Kandemir, N. Vijaykrishnan, M.J. Irwin, and H.S Kim. Experimental evaluation of energy behavior of iteration space tiling, LCPC 2000, Yorktown Heights, NY, 2000, pp. 142–157.
-
(2000)
LCPC 2000
, pp. 142-157
-
-
Kandemir, M.1
Vijaykrishnan, N.2
Irwin, M.J.3
Kim, H.S.4
-
39
-
-
10844232335
-
Fast greedy weighted fusion
-
K. Kennedy. Fast greedy weighted fusion. Int. J. Parallel Programming, Vol. 29, No. 5, 2001, pp. 463–491.
-
(2001)
Int. J. Parallel Programming
, vol.29
, Issue.5
, pp. 463-491
-
-
Kennedy, K.1
-
40
-
-
0030679033
-
An approach for quantitative analysis of application-specific dataflow architectures
-
B. Kienhuis, E. Deprettere, K.A. Vissers and P. Van Der Wolf. An approach for quantitative analysis of application-specific dataflow architectures. Proc. Int. Conf. on Application-Specific Syst., Architectures and Processors (ASAP’97), pp. 338–349, 1997.
-
(1997)
Proc. Int. Conf. on Application-Specific Syst., Architectures and Processors (ASAP’97)
, pp. 338-349
-
-
Kienhuis, B.1
Deprettere, E.2
Vissers, K.A.3
Van Der Wolf, P.4
-
41
-
-
0040291388
-
The Click Modular Router
-
E. Kohler, R. Morris, B. Chen, J. Jannotti, and M. Kaashoek. The Click Modular Router. ACM Trans. on Computer Syst., Vol. 18, No. 3, pp. 263–297, August 2000.
-
(2000)
ACM Trans. on Computer Syst.
, vol.18
, Issue.3
, pp. 263-297
-
-
Kohler, E.1
Morris, R.2
Chen, B.3
Jannotti, J.4
Kaashoek, M.5
-
42
-
-
77954715598
-
-
Technical Report RR- 4715, IRISA, Environnement de spécification de programmes réactifs synchrones (ESPRESSO
-
P. Le Guernic, J.-P. Talpin, and J.-C. Le Lann. Polychrony for system design. Technical Report RR- 4715, IRISA, Environnement de spécification de programmes réactifs synchrones (ESPRESSO), June 2003.
-
(2003)
Polychrony for System Design
-
-
Le Guernic, P.1
Talpin, J.-P.2
Le Lann, J.-C.3
-
44
-
-
0001465739
-
Maximizing loop parallelism and improving data locality via loop fusion and distribution, languages and compilers for parallel computing
-
Portland, Oregon
-
K. McKinley and K. Kennedy. Maximizing loop parallelism and improving data locality via loop fusion and distribution, languages and compilers for parallel computing, 6th Int. Workshop, Portland, Oregon, 1993, pp. 301–320.
-
(1993)
6Th Int. Workshop
, pp. 301-320
-
-
McKinley, K.1
Kennedy, K.2
-
45
-
-
0003578795
-
Object oriented software construction
-
C.A.R. Hoare, Ed., Prentice Hall International, Inc., Englewood Cliffs, NJ
-
Bertrand Meyer. Object oriented software construction. In C.A.R. Hoare, Ed., Series in Computer Science. Prentice Hall International, Inc., Englewood Cliffs, NJ, 1988.
-
(1988)
Series in Computer Science
-
-
Meyer, B.1
-
46
-
-
0036857174
-
Developing architectural platforms: A disciplined approach
-
November/December
-
A. Mihal, C. Kulkarni, M. Moskewicz, M. Tsai, N. Shah, S. Weber, Y. Jin, K. Keutzer, C. Sauer, K. Vissers, and S. Malik. Developing architectural platforms: a disciplined approach, IEEE Design and Test of Computers, Vol. 19, No. 6, pp. 6–16, November/December 2002.
-
(2002)
IEEE Design and Test of Computers
, vol.19
, Issue.6
, pp. 6-16
-
-
Mihal, A.1
Kulkarni, C.2
Moskewicz, M.3
Tsai, M.4
Shah, N.5
Weber, S.6
Jin, Y.7
Keutzer, K.8
Sauer, C.9
Vissers, K.10
Malik, S.11
-
47
-
-
84951790574
-
Automatic synthesis of a parallel architecture for Kalman filtering using MMAlpha
-
Edmonton, Canada
-
A. Mozipo, D. Massicote, P. Quinton, and T. Risset. Automatic synthesis of a parallel architecture for Kalman filtering using MMAlpha. IEEE Canadian Conf. on Electrical and Comput. Eng., Edmonton, Canada, May 1999.
-
(1999)
IEEE Canadian Conf. on Electrical and Comput. Eng.
-
-
Mozipo, A.1
Massicote, D.2
Quinton, P.3
Risset, T.4
-
48
-
-
18844427226
-
Broadcom Calisto: A multi-channel multi-service communication platform
-
J. Nickolls, L.J. Madar III, S. Johnson, V. Rustagi, K. Unger, and M. Choudhury, Broadcom Calisto: a multi-channel multi-service communication platform, Hot-Chips Symp., 2002.
-
(2002)
Hot-Chips Symp.
-
-
Nickolls, J.1
Madar, L.J.2
Johnson, S.3
Rustagi, V.4
Unger, K.5
Choudhury, M.6
-
49
-
-
85056981497
-
-
T. Pascalin Amagbegnon, P. Le Guernic, H. Marchand, and E. Rutten. Signal. Lecture Notes in Computer Science, Vol. 891, pp. 113–, 1995.
-
(1995)
Signal. Lecture Notes in Computer Science
, vol.891
, pp. 113
-
-
Pascalin Amagbegnon, T.1
Le Guernic, P.2
Marchand, H.3
Rutten, E.4
-
50
-
-
85056977215
-
-
Philips Semiconductors, B.V., Functional Overview
-
Philips Semiconductors, B.V. Nexperia pnx8500: Home entertainment engine. Functional Overview, 2000. Available at http://www.semiconductors.philips.com/nexperia.
-
(2000)
Nexperia Pnx8500: Home Entertainment Engine
-
-
-
51
-
-
15544378035
-
Functional verification of systems on chip (SOCs) — practices, issues and challenges
-
(Synplicity, Inc.)(IITBombay)(Futjitsu Laboratories), January 7–11, Bangalore, India
-
S.K. Roy (Synplicity, Inc.), S. Ramesh, S. Chakraborty (IITBombay), T. Nakata, and S.P. Rajan (Futjitsu Laboratories). Functional verification of systems on chip (SOCs) — practices, issues and challenges. ASP-DAC/VLSI Design 2002, January 7–11, 2002, Bangalore, India, pp. 11–.
-
(2002)
ASP-DAC/VLSI Design 2002
, pp. 11
-
-
Roy, S.K.1
Ramesh, S.2
Chakraborty, S.3
Nakata, T.4
Rajan, S.P.5
-
52
-
-
84943625538
-
Panel probes SOC problems, solutions
-
February
-
M. Scott, J. Dickerson, and B. Payne. Panel probes SOC problems, solutions. EE Design, February 2002. http://www.eedesign.com/news/OEG20000202S0044.
-
(2002)
EE Design
-
-
Scott, M.1
Dickerson, J.2
Payne, B.3
-
53
-
-
0003703503
-
-
Master’s thesis, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley
-
N. Shah, Understanding network processors. Master’s thesis, Department of Electrical Engineering and Computer Sciences, University of California-Berkeley, September 2001.
-
(2001)
Understanding Network Processors
-
-
Shah, N.1
-
54
-
-
74549165498
-
-
SystemC Verification Working Group, Technical Report, Open SystemC Initiative (OSCI
-
SystemC Verification Working Group. SystemC verification standard specification. Technical Report, Open SystemC Initiative (OSCI), November 2002. Available at http://www.systemc.org.
-
(2002)
Systemc Verification Standard Specification
-
-
-
55
-
-
85056942791
-
-
Teja Technologies, White Paper
-
Teja Technologies, IPv4 forwarding application performance, White Paper, July 2002. Available at http://www.teja.com/library/ip4_whitepaper.html.
-
(2002)
Ipv4 Forwarding Application Performance
-
-
-
56
-
-
79952781954
-
A benchmarking methodology for network processors
-
Cambridge, MA
-
M. Tsai, C. Kulkarni, C. Sauer, N. Shah, and K. Keutzer, A benchmarking methodology for network processors, First Workshop on Network Processors at the 8th Int. Symp. on High Performance Computer Architecture (HPCA8), Cambridge, MA, February 2002.
-
(2002)
First Workshop on Network Processors at the 8Th Int. Symp. on High Performance Computer Architecture (HPCA8)
-
-
Tsai, M.1
Kulkarni, C.2
Sauer, C.3
Shah, N.4
Keutzer, K.5
-
57
-
-
1442292440
-
-
Verisity Design, Inc, White Paper
-
Verisity Design, Inc. Spec-based verification. White Paper, 1999. Available at http://www.verisity.com/resources/whitepaper/.
-
(1999)
Spec-Based Verification
-
-
-
59
-
-
85056977028
-
-
Verisity Design, Inc, Technical Report, Verisity Design, Inc
-
Verisity Design, Inc. The evolution of verification methodology. Technical Report, Verisity Design, Inc., 2001.
-
(2001)
The Evolution of Verification Methodology
-
-
-
61
-
-
0024627841
-
A method for generating weighted random test patterns
-
J.A. Waicukauski, E. Lindbloom, E.B. Eichelberger, and O.P. Forlenza. A method for generating weighted random test patterns. IBM J. Res. and Dev., Vol. 33, No. 2, pp. 149–161, March 1989.
-
(1989)
IBM J. Res. and Dev.
, vol.33
, Issue.2
, pp. 149-161
-
-
Waicukauski, J.A.1
Lindbloom, E.2
Eichelberger, E.B.3
Forlenza, O.P.4
-
64
-
-
0032303141
-
Formalized methodology for data reuse exploration for low-power hierarchical memory mappings
-
Dec
-
S. Wuytack, J.P. Diguet, F. Catthoor, and H. De Man. Formalized methodology for data reuse exploration for low-power hierarchical memory mappings, IEEE Trans. on VLSI Syst., Special Issue ISLPED’97, Vol. 4, No. 6, pp. 529-537, Dec. 1998.
-
(1998)
IEEE Trans. on VLSI Syst., Special Issue ISLPED’97
, vol.4
, Issue.6
, pp. 529-537
-
-
Wuytack, S.1
Diguet, J.P.2
Catthoor, F.3
De Man, H.4
|