Hardware transactional memory for GPU architectures

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 296-307

  Fung, Wilson W L ^a   Singh, Inderpreet ^a   Brownsword, Andrew ^a   Aamodt, Tor M ^a  

^a UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; ATOMIC OPERATION; BLOOM FILTERS; BROADCAST COMMUNICATION; CACHE COHERENCY; CONCURRENT THREADS; CONCURRENT TRANSACTIONS; CONFLICT DETECTION; GRAPHICS PROCESSOR UNITS; MEMORY ACCESS; MEMORY LOCATIONS; MULTIPLE THREADS; NOVEL HARDWARE; ON-CHIP STORAGE; SCRATCH PAD MEMORY; THREAD-LEVEL PARALLELISM; TRANSACTIONAL MEMORY; VALUE-BASED; WORKGROUPS;

COMMUNICATION; LOCKS (FASTENERS); STORAGE ALLOCATION (COMPUTER);

PROGRAM PROCESSORS;

EID: 84858761190     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155655     Document Type: Conference Paper

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