The NoX router

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 36-46

  Hayenga, Mitchell ^a   Lipasti, Mikko ^a  

^a University of Wisconsin Madison   (United States)

Author keywords

arbitration; multi core; on chip networks; routing

Indexed keywords

ACCURATE CHANNELS; ARBITRATION; CODING SCHEME; CROSSBAR ARCHITECTURE; CYCLE-ACCURATE SIMULATION; ENERGY DELAY PRODUCT; EXCLUSIVE-OR; FLOORPLANS; LOW LATENCY; MARGINAL COSTS; MULTI CORE; NETWORK THROUGHPUT; ON-CHIP NETWORKS; PERFORMANCE EVALUATION; POWER BUDGETS; POWER CONSUMING; POWER EFFICIENT; POWER MODEL; ROUTING; SINGLE CYCLE; TRAFFIC PATTERN;

COMPUTER SIMULATION; MODELS; NETWORK ARCHITECTURE;

ROUTERS;

EID: 84858756043     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155626     Document Type: Conference Paper

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