Efficient hardware accelerators for the computation of Tchebichef moments

IEEE Transactions on Circuits and Systems for Video Technology

Volumn 22, Issue 3, 2012, Pages 414-425

  Chang, Kah Hyong ^a   Paramesran, Raveendran ^a   Asli, Barmak Honarvar Shakibaei ^a   Lim, Chern Loon ^a  

^a UNIVERSITY OF MALAYA   (Malaysia)

Author keywords

Accelerator architectures; digital filters; large dynamic range; moment methods

Indexed keywords

ACCELERATOR ARCHITECTURES; ACCELERATOR DESIGN; AREA EFFICIENT; COMPUTATION ENGINE; DIRECT METHOD; FIELD-PROGRAMMABLE GATE ARRAY IMPLEMENTATIONS; FILTER LOAD; FUNCTIONAL TEST; HARDWARE ACCELERATORS; HARDWARE RESOURCES; HIGH DEFINITION VIDEO; HIGH OPERATING FREQUENCY; HIGH RESOLUTION IMAGE; LARGE DYNAMIC RANGE; MATRIX MULTIPLICATION; MOMENT COMPUTATIONS; MULTI-CHIP; MULTI-PLATFORM; ON CHIPS; REAL TIME; SINGLE-CHIP; SYNTHETIC IMAGES; TCHEBICHEF MOMENTS; TEST DATA; TIME MULTIPLEXED;

DESIGN; DIGITAL FILTERS; METHOD OF MOMENTS; PIXELS;

ACCELERATION;

EID: 84858012271     PISSN: 10518215     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSVT.2011.2163980     Document Type: Article

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