Exploring the limits of GPGPU scheduling in control flow bound applications

Transactions on Architecture and Code Optimization

Volumn 8, Issue 4, 2012, Pages

  Malits, Roman ^a   Bolotin, Evgeny ^b   Kolodny, Avinoam ^a   Mendelson, Avi ^c  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^b INTEL CORPORATION   (Israel)

^c MICROSOFT RESEARCH   (United States)

Author keywords

GPGPU; Parallel machines; Scheduling algorithm

Indexed keywords

CONTROL FLOWS; DATA PARALLEL; GENERAL PURPOSE; GLOBAL SCHEDULING; GPGPU; HARDWARE UTILIZATION; HIGH RATE; IN-CONTROL; INHERENT LIMITATIONS; MACHINE UTILIZATION; MATRIX MULTIPLICATION; MEMORY ACCESS PATTERNS; PARALLEL GRAPH ALGORITHMS; PARALLEL MACHINE; PERFORMANCE GAIN; PERFORMANCE IMPROVEMENTS; ROOT CAUSE; RUNNING CONTROL; SCHEDULING MECHANISM; SCHEDULING METHODS; SHARED MEMORIES; THREAD SCHEDULING;

BENCHMARKING; OPTIMIZATION; PROGRAM PROCESSORS; SCHEDULING; SCHEDULING ALGORITHMS;

MULTITASKING;

EID: 84857873786     PISSN: 15443566     EISSN: 15443973     Source Type: Journal    
DOI: 10.1145/2086696.2086708     Document Type: Article

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