-
1
-
-
61549132828
-
High-density through silicon vias for 3-D LSIs
-
Jan.
-
M. Koyanagi, T. Fukushima, and T. Tanaka, "High-density through silicon vias for 3-D LSIs," Proc. IEEE, vol. 97, no. 1, pp. 49-59, Jan. 2009.
-
(2009)
Proc. IEEE
, vol.97
, Issue.1
, pp. 49-59
-
-
Koyanagi, M.1
Fukushima, T.2
Tanaka, T.3
-
2
-
-
73349133689
-
Electrical modeling and characterization of through silicon via for 3-D ICs
-
Jan.
-
G. Katti, M. Stucchi, K. De Meyer, andW. Dehaena, "Electrical modeling and characterization of through silicon via for 3-D ICs," IEEE Trans. Electron Devices, vol. 57, no. 1, pp. 256-262, Jan. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.1
, pp. 256-262
-
-
Katti, G.1
Stucchi, M.2
De Meyer, K.3
Dehaena, W.4
-
3
-
-
84857454206
-
Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects
-
Jun.
-
T. Bandyopadhyay, K. J. Han, D. Chung, R. Chatterjee, M. Swaminathan, and R. Tummala, "Rigorous electrical modeling of through silicon vias (TSVs) with MOS capacitance effects," IEEE Trans. Compon. Packag. Manufac. Technol., vol. 1, no. 6, pp. 893-903, Jun. 2011.
-
(2011)
IEEE Trans. Compon. Packag. Manufac. Technol.
, vol.1
, Issue.6
, pp. 893-903
-
-
Bandyopadhyay, T.1
Han, K.J.2
Chung, D.3
Chatterjee, R.4
Swaminathan, M.5
Tummala, R.6
-
4
-
-
77952742120
-
Multiphysics characterization of transient electrothermomechanical responses of through-silicon via applied with a periodic voltage pulse
-
Jun.
-
X. P. Wang, W. Y. Yin, and S. He, "Multiphysics characterization of transient electrothermomechanical responses of through-silicon via applied with a periodic voltage pulse," IEEE Trans. Electron Devices, vol. 57, no. 6, pp. 1382-1389, Jun. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.6
, pp. 1382-1389
-
-
Wang, X.P.1
Yin, W.Y.2
He, S.3
-
5
-
-
77952744147
-
Progress review of electromagnetic compatibility analysis technologies for package, printed circuit boards, and novel interconnects
-
May
-
E. P. Li, X. C.Wei, A. C. Cangellaris, E. X. Liu, Y. J. Zhang, M. D'Amore, J. Kim, and T. Sudo, "Progress review of electromagnetic compatibility analysis technologies for package, printed circuit boards, and novel interconnects," IEEE Trans. Electromagn. Compat., vol. 52, no. 2, pp. 248-265, May 2010.
-
(2010)
IEEE Trans. Electromagn. Compat.
, vol.52
, Issue.2
, pp. 248-265
-
-
Li, E.P.1
Wei, X.C.2
Cangellaris, A.C.3
Liu, E.X.4
Zhang, Y.J.5
D'amore, M.6
Kim, J.7
Sudo, T.8
-
6
-
-
73249131982
-
8 Gb 3-D DDR3 DRAM using through-siliconvia technology
-
Jan.
-
U. Kang, H.-J. Chung, S. Heo, D.-H. Park, H. Lee, J. H. Kim, S.-H. Ahn, S.-H. Cha, J. Ahn, D. Kwon, J.-W. Lee, H.-S. Joo,W.-S. Kim, D. H. Jang, N. S. Kim, J.-H. Choi, T.-G. Chung, J.-H. Yoo, J. S. Yoo, J. S. Choi, C. Kim, and Y.-H. Jun, "8 Gb 3-D DDR3 DRAM using through-siliconvia technology," IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 111-119, Jan. 2010.
-
(2010)
IEEE J. Solid-State Circuits
, vol.45
, Issue.1
, pp. 111-119
-
-
Kang, U.1
Chung, H.-J.2
Heo, S.3
Park, D.-H.4
Lee, H.5
Kim, J.H.6
Ahn, S.-H.7
Cha, S.-H.8
Ahn, J.9
Kwon, D.10
Lee, J.-W.11
Joo, H.-S.12
Kim, W.-S.13
Jang, D.H.14
Kim, N.S.15
Choi, J.-H.16
Chung, T.-G.17
Yoo, J.-H.18
Yoo, J.S.19
Choi, J.S.20
Kim, C.21
Jun, Y.-H.22
more..
-
7
-
-
79959316022
-
Electromigration performance of through silicon via (TSV)-A modeling approach
-
Sep.-Nov.
-
Y.C. Tan,C.M. Tan,X.W. Zhang, T. C. Chai, andD.Q.Yu, " Electromigration performance of through silicon via (TSV)-A modeling approach," Microelectron. Reliab., vol. 50, no. 9-11, pp. 1336-1340, Sep.-Nov. 2010.
-
(2010)
Microelectron. Reliab.
, vol.50
, Issue.9-11
, pp. 1336-1340
-
-
Tan, Y.C.1
Tan, C.M.2
Zhang, X.W.3
Chai, T.C.4
Yu, D.Q.5
-
8
-
-
69549088334
-
Carbon nanomaterials for next-generation interconnects and passive: Physics, status, and prospects
-
Sep.
-
H. Li, C. Xu, N. Srivastava, and K. Banerjee, "Carbon nanomaterials for next-generation interconnects and passive: Physics, status, and prospects," IEEE Trans. Electron Devices, vol. 56, no. 9, pp. 1799-1821, Sep. 2009.
-
(2009)
IEEE Trans. Electron Devices
, vol.56
, Issue.9
, pp. 1799-1821
-
-
Li, H.1
Xu, C.2
Srivastava, N.3
Banerjee, K.4
-
9
-
-
33646248381
-
Compact physical models for multiwall carbon-nanotube interconnects
-
May
-
A. Naeemi and J. D. Meindl, "Compact physical models for multiwall carbon-nanotube interconnects," IEEE Electron Device Lett., vol. 27, no. 5, pp. 338-340, May 2006.
-
(2006)
IEEE Electron Device Lett.
, vol.27
, Issue.5
, pp. 338-340
-
-
Naeemi, A.1
Meindl, J.D.2
-
10
-
-
2342466950
-
Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes
-
DOI 10.1109/TNANO.2002.806823
-
P. J. Burke, "Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes," IEEE Trans. Nanotechnol., vol. 1, no. 3, pp. 129-144, Sep. 2002. (Pubitemid 43987426)
-
(2002)
IEEE Transactions on Nanotechnology
, vol.1
, Issue.3
, pp. 129-144
-
-
Burke, P.J.1
-
11
-
-
70350183749
-
High-frequency analysis of carbon nanotube interconnects and implications for on-chip inductor design
-
Oct.
-
H. Li and K. Banerjee, "High-frequency analysis of carbon nanotube interconnects and implications for on-chip inductor design," IEEE Trans. Electron Devices, vol. 56, no. 10, pp. 2202-2214, Oct. 2009.
-
(2009)
IEEE Trans. Electron Devices
, vol.56
, Issue.10
, pp. 2202-2214
-
-
Li, H.1
Banerjee, K.2
-
12
-
-
67349165844
-
Crosstalk prediction of single- and double-walled carbon-nanotube (SWCNT/DWCNT) bundle interconnects
-
Apr.
-
S. N. Pu, W. Y. Yin, J. F. Mao, and Q. H. Liu, "Crosstalk prediction of single- and double-walled carbon-nanotube (SWCNT/DWCNT) bundle interconnects," IEEE Trans. Electron Devices, vol. 56, no. 4, pp. 560-568, Apr. 2009.
-
(2009)
IEEE Trans. Electron Devices
, vol.56
, Issue.4
, pp. 560-568
-
-
Pu, S.N.1
Yin, W.Y.2
Mao, J.F.3
Liu, Q.H.4
-
13
-
-
84859891508
-
ACCNT - A metallic-CNT-tolerant design methodology for carbon-nanotube VLSI: Concept and experimental demonstration
-
Dec.
-
A. Lin, N. Patil, H.Wei, S. Mitra, and H.-S. P.Wong, "ACCNT-a metallic-CNT-tolerant design methodology for carbon-nanotube VLSI: Concept and experimental demonstration," IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 2969-2978, Dec. 2009.
-
(2009)
IEEE Trans. Electron Devices
, vol.56
, Issue.12
, pp. 2969-2978
-
-
Lin, A.1
Patil, N.2
Wei, H.3
Mitra, S.4
Wong, H.-S.P.5
-
14
-
-
62449245505
-
New electron-waveguidebased modeling for carbon nanotube interconnects
-
Mar.
-
M. S. Sarto, A. Tamburrano, andM. D'Amore, "New electron- waveguidebased modeling for carbon nanotube interconnects," IEEE Trans. Nanotechnol., vol. 8, no. 2, pp. 214-225, Mar. 2009.
-
(2009)
IEEE Trans. Nanotechnol.
, vol.8
, Issue.2
, pp. 214-225
-
-
Sarto, M.S.1
Tamburrano, A.2
D'amore, M.3
-
15
-
-
75449100521
-
Single-conductor transmission-line model of multiwall carbon nanotubes
-
Jan.
-
M. S. Sarto and A. Tamburrano, "Single-conductor transmission-line model of multiwall carbon nanotubes," IEEE Trans. Nanotechnol., vol. 9, no. 1, pp. 82-92, Jan. 2010.
-
(2010)
IEEE Trans. Nanotechnol.
, vol.9
, Issue.1
, pp. 82-92
-
-
Sarto, M.S.1
Tamburrano, A.2
-
16
-
-
77952742241
-
Fast transient analysis of next-generation interconnects based on carbon nanotubes
-
May
-
M. D'Amore, M. S. Sarto, and A. Tamburrano, "Fast transient analysis of next-generation interconnects based on carbon nanotubes," IEEE Trans. Electromagn. Compat., vol. 52, no. 2, pp. 496-503, May 2010.
-
(2010)
IEEE Trans. Electromagn. Compat.
, vol.52
, Issue.2
, pp. 496-503
-
-
D'amore, M.1
Sarto, M.S.2
Tamburrano, A.3
-
17
-
-
21244470717
-
Electrical properties of carbon nanotube bundles for future via interconnects
-
DOI 10.1143/JJAP.44.1626
-
M. Nihei, A. Kawabata, D. Kondo, M. Horibe, S. Sato, and Y. Awano, "Electrical properties of carbon nanotube bundles for future via interconnects," Jpn. J. Appl. Phys., vol. 44, pp. 1626-1628, Apr. 2005. (Pubitemid 40892534)
-
(2005)
Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
, vol.44
, Issue.4 A
, pp. 1626-1628
-
-
Nihei, M.1
Kawabata, A.2
Kondo, D.3
Horibe, M.4
Sato, S.5
Awano, Y.6
-
18
-
-
74749103724
-
Multiwall carbon nanotube vias: An effective TL model for EMC oriented analysis
-
Austin, TX, Aug.
-
M. S. Sarto and A. Tamurrano, "Multiwall carbon nanotube vias: An effective TL model for EMC oriented analysis," in Proc. IEEE Int. Symp. Electromagn. Compat. (ISEMC), Austin, TX, Aug. 2009, pp. 17-21.
-
(2009)
Proc. IEEE Int. Symp. Electromagn. Compat. (ISEMC)
, pp. 17-21
-
-
Sarto, M.S.1
Tamurrano, A.2
-
19
-
-
77954985865
-
SPICE-model of multiwall carbon nanotube through-hole vias
-
Beijing, Apr.
-
M. D'Amore, M. S. Sarto, and A. Tamburrano, "SPICE-model of multiwall carbon nanotube through-hole vias," in Proc. Asia-Pacific Symp. Electromagn. Compat. (APEMC), Beijing, Apr. 2010, pp. 1104-1107.
-
(2010)
Proc. Asia-Pacific Symp. Electromagn. Compat. (APEMC)
, pp. 1104-1107
-
-
D'amore, M.1
Sarto, M.S.2
Tamburrano, A.3
-
20
-
-
81255147788
-
Pursuit of future interconnect technology with aligned carbon nanotube arrays
-
Mar.
-
Y. Chai, M. Sun, Z. Xiao, Y. Li, M. Zhang, and P. C. H. Chan, "Pursuit of future interconnect technology with aligned carbon nanotube arrays," IEEE Nano Technol. Mag., vol. 5, no. 1, pp. 22-26, Mar. 2011.
-
(2011)
IEEE Nano Technol. Mag.
, vol.5
, Issue.1
, pp. 22-26
-
-
Chai, Y.1
Sun, M.2
Xiao, Z.3
Li, Y.4
Zhang, M.5
Chan, P.C.H.6
-
21
-
-
55849130732
-
Selective growth of carbon nanotube for via interconnects by oxidation and selective reduction of catalyst
-
Jun.
-
S. Lee, S. Moon, H. S. Yoon, X. Wang, D. W. Kim, I.-S. Yeo, U. Chung, J.-T. Mon, and J. Chung, "Selective growth of carbon nanotube for via interconnects by oxidation and selective reduction of catalyst," Appl. Phys. Lett., vol. 93, no. 18, 182106, Jun. 2009.
-
(2009)
Appl. Phys. Lett.
, vol.93
, Issue.18
, pp. 182106
-
-
Lee, S.1
Moon, S.2
Yoon, H.S.3
Wang, X.4
Kim, D.W.5
Yeo, I.-S.6
Chung, U.7
Mon, J.-T.8
Chung, J.9
-
22
-
-
78650094325
-
Carbon nanotube array vias for interconnect applications
-
May/Jun.
-
J.-H. Ting, C.-C. Chiu, and F.-Y. Huang, "Carbon nanotube array vias for interconnect applications," J. Vac. Sci. Technol. B, vol. 27, no. 3, pp. 1086-1092, May/Jun. 2009.
-
(2009)
J. Vac. Sci. Technol. B
, vol.27
, Issue.3
, pp. 1086-1092
-
-
Ting, J.-H.1
Chiu, C.-C.2
Huang, F.-Y.3
-
23
-
-
34547445650
-
Aligned carbon nanotubes for through-wafer interconnects
-
Jun.
-
T. Xu, Z. Wang, J. Miao, X. Chen, and C. M. Tan, "Aligned carbon nanotubes for through-wafer interconnects," Appl. Phys. Lett., vol. 91, no. 4, 042108, Jun. 2009.
-
(2009)
Appl. Phys. Lett.
, vol.91
, Issue.4
, pp. 042108
-
-
Xu, T.1
Wang, Z.2
Miao, J.3
Chen, X.4
Tan, C.M.5
-
24
-
-
70449769320
-
Through silicon vias filled with planarized carbon nanotube bundles
-
(6 pp.), Nov.
-
T. Wang, K. Jeppson, N. Olofesson, E. B. Eleanor, and J. Liu, "Through silicon vias filled with planarized carbon nanotube bundles," Nanotechnol., vol. 20, no. 48, 485203 (6 pp.), Nov. 2009.
-
(2009)
Nanotechnol.
, vol.20
, Issue.48
, pp. 485203
-
-
Wang, T.1
Jeppson, K.2
Olofesson, N.3
Eleanor, E.B.4
Liu, J.5
-
25
-
-
78650018928
-
Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs
-
Dec.
-
C. Xu, H. Li, R. Suaya, and K. Banerjee, "Compact AC modeling and performance analysis of through-silicon vias in 3-D ICs," IEEE Trans. Electron Devices, vol. 57, no. 12, pp. 3405-3417, Dec. 2010.
-
(2010)
IEEE Trans. Electron Devices
, vol.57
, Issue.12
, pp. 3405-3417
-
-
Xu, C.1
Li, H.2
Suaya, R.3
Banerjee, K.4
-
26
-
-
79960901040
-
Highfrequency scalable electrical model and analysis of a through silicon via (TSV)
-
Feb.
-
J. Kim, J. S. Pak, J. Cho, E. Song, J. Cho, H. Kim, T. Song, J. Lee, H. Lee, K. Park, S. Yang, M.-S. Suh, K.-Y. Byun, and J. Kim, "Highfrequency scalable electrical model and analysis of a through silicon via (TSV)," IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 181-195, Feb. 2011.
-
(2011)
IEEE Trans. Compon. Packag. Manuf. Technol.
, vol.1
, Issue.2
, pp. 181-195
-
-
Kim, J.1
Pak, J.S.2
Cho, J.3
Song, E.4
Cho, J.5
Kim, H.6
Song, T.7
Lee, J.8
Lee, H.9
Park, K.10
Yang, S.11
Suh, M.-S.12
Byun, K.-Y.13
Kim, J.14
-
27
-
-
84857458016
-
-
[Online]
-
Wikipedia. [Online]. Available: http://enwikipedia.org
-
-
-
-
28
-
-
0026908091
-
S-parameter-based IC interconnect transmission line characterization
-
DOI 10.1109/33.159877
-
W. R. Eisenstadt and Y. Eo, "S-parameter-based IC interconnect transmission line characterization," IEEE Trans. Compon. Hybrids Manuf. Technol., vol. 15, no. 4, pp. 483-490, Aug. 1992. (Pubitemid 23555802)
-
(1992)
IEEE transactions on components, hybrids, and manufacturing technology
, vol.15
, Issue.4
, pp. 483-490
-
-
Eisenstadt, W.R.1
Eo, Y.2
-
29
-
-
80155176733
-
Modeling and analysis of through-silicon via (TSV) noise coupling and suppreession using a guard ring
-
Feb.
-
J. Cho, E. Song, K. Yoon, J. S. Pak, J. Kim, W. Lee, T. Song, K. Kim, J. Lee, H. Lee, K. Park, S. Yang, M. Suh, K. Byun, and J. Kim, "Modeling and analysis of through-silicon via (TSV) noise coupling and suppreession using a guard ring," IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 220-233, Feb. 2011.
-
(2011)
IEEE Trans. Compon. Packag. Manuf. Technol.
, vol.1
, Issue.2
, pp. 220-233
-
-
Cho, J.1
Song, E.2
Yoon, K.3
Pak, J.S.4
Kim, J.5
Lee, W.6
Song, T.7
Kim, K.8
Lee, J.9
Lee, H.10
Park, K.11
Yang, S.12
Suh, M.13
Byun, K.14
Kim, J.15
-
30
-
-
0029500058
-
Inductance calculations; Modeling and equations
-
Atlanta, GA, Aug.
-
F. B. J. Leferink, "Inductance calculations; modeling and equations," in Proc. IEEE Symp. Electromagn. Compat., Atlanta, GA, Aug. 1995, pp 16-22.
-
(1995)
Proc. IEEE Symp. Electromagn. Compat.
, pp. 16-22
-
-
Leferink, F.B.J.1
-
32
-
-
80155196172
-
PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip-PDN models
-
Feb.
-
J. S. Pak, J. Kim, J. Cho, K. Kim, T. Song, S. Ahn, J. Lee, H. Lee, K. Park, and J. Kim, "PDN impedance modeling and analysis of 3D TSV IC by using proposed P/G TSV array model based on separated P/G TSV and chip-PDN models," IEEE Trans. Compon. Packag. Manuf. Technol., vol. 1, no. 2, pp. 208-219, Feb. 2011.
-
(2011)
IEEE Trans. Compon. Packag. Manuf. Technol.
, vol.1
, Issue.2
, pp. 208-219
-
-
Pak, J.S.1
Kim, J.2
Cho, J.3
Kim, K.4
Song, T.5
Ahn, S.6
Lee, J.7
Lee, H.8
Park, K.9
Kim, J.10
-
33
-
-
36348938807
-
Electromagnetic-thermal characterization of on on-chip coupled (A)symmetrical interconnects
-
DOI 10.1109/TADVP.2007.908016
-
W.-Y. Yin, K. Kang, and J.-F. Mao, "Electromagnetic-thermal characterization of on on-chip coupled (a)symmetrical interconnects," IEEE Trans. Adv. Packag., vol. 30, no. 4, pp. 851-863, Nov. 2007. (Pubitemid 350148410)
-
(2007)
IEEE Transactions on Advanced Packaging
, vol.30
, Issue.4
, pp. 851-863
-
-
Yin, W.-Y.1
Kang, K.2
Mao, J.-F.3
-
34
-
-
79955970977
-
Crosstalk evaluation, suppression and modeling in 3-D through-siliconvia (TSV) network
-
Munich, Germany, Nov.
-
Z. Xu, A. Beece, D. Zhang, Q. Chen, K. Chen, K. Rose, and J. Q. Lu, "Crosstalk evaluation, suppression and modeling in 3-D through-siliconvia (TSV) network," in Proc. IEEE Int. 3D System Integration Conf., Munich, Germany, Nov. 2010.
-
(2010)
Proc. IEEE Int. 3D System Integration Conf.
-
-
Xu, Z.1
Beece, A.2
Zhang, D.3
Chen, Q.4
Chen, K.5
Rose, K.6
Lu, J.Q.7
|