Distributed power network co-design with on-chip power supplies and decoupling capacitors

International Workshop on System Level Interconnect Prediction, SLIP

Volumn , Issue , 2011, Pages

  Kose, Selcuk ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CO-DESIGNS; DECOUPLING CAPACITOR; DISTRIBUTED POWER; ON CHIPS; POWER DELIVERY NETWORK; POWER DISTRIBUTION NETWORK; POWER NETWORKS; POWER SUPPLY; POWER-SUPPLY NOISE;

CAPACITORS; ELECTRIC NETWORK ANALYSIS; ELECTRIC POWER SYSTEM INTERCONNECTION; ELECTRIC POWER TRANSMISSION; SYSTEMS ANALYSIS;

DISTRIBUTED COMPUTER SYSTEMS;

EID: 84857223045     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/SLIP.2011.6135434     Document Type: Conference Paper

References (16)

1. R. Jakushokas, M. Popovich, A. V. Mezhiba, S. Kose, and E. G. Friedman, Power Distribution Networks with On-Chip Decoupling Capacitors, Second Edition, Springer, 2011.
2. S. Pant, D. Blaauw, and E. Chiprout, "Power Grid Physics and Implications for CAD," IEEE Design and Test of Computers, Vol. 24, No. 3, pp. 246-254, May 2007. (Pubitemid 47322976)
3. P. Larsson, "di/dt Noise in CMOS Integrated Circuits," Analog Integrated Circuits and Signal Processing, Vol. 14, No. 2, pp. 113-129, September 1997. (Pubitemid 127504708)
4. S. Kose and E. G. Friedman, "Fast Algorithms for IR Voltage Drop Analysis Exploiting Locality," Proceedings of the IEEE/ACM Design Automation Conference, pp. 996-1001, June 2011.
5. L. Smith et al., "Power Distribution System Design Methodology and Capacitor Selection for Modern CMOS Technology," IEEE Transactions on Advanced Packaging, Vol. 22, No. 3, pp. 284-291, August 1999. (Pubitemid 30559648)
6. H. H. Chen and S. E. Schuster, "On-Chip Decoupling Capacitor Optimization for High-Performance VLSI Design," Proceedings of the IEEE International Symposium on VLSI Technology, pp. 99-103, May/June 1995.
7. V. Kursun and E. G. Friedman, Multi-Voltage CMOS Circuit Design, Wiley & Sons, 2006.
8. S. Kose and E. G Friedman, "On-Chip Point-of-Load Voltage Regulator for Distributed Power Supplies," Proceedings of the ACM Great Lakes Symposium on VLSI, pp. 377-380, May 2010.
9. S. Kose and E. G Friedman, "An Area Efficient Fully Monolithic Hybrid Voltage Regulator," Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 2718-2721, May/June 2010.
10. P. Hazucha et al., "Area-Efficient Linear Regulator with Ultra-Fast Load Regulation," IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, pp. 933-940, April 2005.
11. M. Popovich, M. Sotman, A. Kolodny, and E. G. Friedman, "Effective Radii of On-Chip Decoupling Capacitors," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 7, pp. 894-907, July 2008.
12. B. Amelifard and M. Pedram, "Area-Efficient Linear Regulator with Ultra-Fast Load Regulation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 6, pp. 888-900, June 2009.
13. W. Kim, M. S. Gupta, G.-Y. Wei, and D. Brooks, "System Level Analysis of Fast, Per-Core DVFS Using On-Chip Switching Regulators," Proceedings of the IEEE International Symposium on High Performance Computer Architecture, pp. 123-134, February 2008.
14. E. Salman, E. G. Friedman, R. M. Secerenau, and O. L. Martin, "Worst Case Power/Ground Noise Estimation Using an Equivalent Transition Time for Resonance," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 56, No. 5, pp. 997-1004, May 2009.
15. A. Todri, M. Marek-Sadowska, F. Maire, and C. Matheron, "A Study of Decoupling Capacitor Effectiveness in Power and Ground Grid Networks," Proceedings of the IEEE International Symposium on Quality Electronic Design, pp. 653-658, March 2009.
16. G. Venezian, "On the Resistance between Two Points on a Grid," American Journal of Physics, Vol. 62, No. 11, pp. 1000-1004, November 1994.