A scalable bandwidth-aware architecture for connected component labeling

Lecture Notes in Electrical Engineering

Volumn 105 LNEE, Issue , 2011, Pages 133-149

  Kumar, Vikram Sampath ^a   Irick, Kevin ^a   Maashri, Ahmed Al ^a   Narayanan, Vijaykrishnan ^a  

^a The Pennsylvania State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH-AWARE; COMPUTING PLATFORM; CONNECTED COMPONENT LABELING; HARDWARE PERFORMANCE; I/O BANDWIDTH; SCALABLE PROCESSORS;

ARCHITECTURE; FIELD PROGRAMMABLE GATE ARRAYS (FPGA); IMAGE PROCESSING;

COMPUTER ARCHITECTURE;

EID: 84856609182     PISSN: 18761100     EISSN: 18761119     Source Type: Book Series    
DOI: 10.1007/978-94-007-1488-5_8     Document Type: Article

References (10)

1. Kumar VS, Irick K, Al Maashri A , Narayanan VK (2010) A Scalable bandwidth aware architecture for connected component labeling, Proceeding ISVLSI
2. Rosenfeld A, Pfaltz J (1966) Sequential operations in digital picture processing. J ACM 13(4):471-494
3. Bailey DG (1991) Raster based region growing. In: Proceedings of the 6th New Zealand image processing workshop, Lower Hutt, New Zealand, August , pp 21-26
4. Ashley R, Ranganathan N (1997) C3L: A chip for connected component labeling. In: the Proceedings of the 10th international conference on VLSI design: VLSI in Multimedia Applications, p 446. 4-7 Jan
5. Alnuweiti HM, Prasanna VK (1992) Parallel architectures and algorithms for image component labeling. IEEE Trans Pattern Anal Machine Intell 14(10):1014-1034
6. Crookes D, Benkrid K (1999) An FPGA implementation of image component labeling. In: Reconfigurable technology: FPGAs for computing and applications, SPIE 3844:17-23. Aug (Pubitemid 30513402)
7. Bailey DG, Johnston CT (2007) Single pass connected components analysis. In: Image and vision computing, New Zealand, Hamilton, New Zealand, pp 282-287. 6, 7 Dec
8. Johnston CT, Bailey DG (2008) FPGA implementation of a single pass connected components algorithm, In: IEEE international symposium on electronic design, test and applications (DELTA 2008), Hong Kong, pp 228-231. 23-25 Jan
9. Jablonski M, Gorgon M (2004) Handel-C implementation of classical component labeling algorithm. In: Euromicro Symposium on Digital System Design (DSD 2004), Rennes, France, 387-393 (31 August-3 September 2004) (Pubitemid 40266701)
10. Appiah K, Hunter A, Dickinson P, Owens J (2008) A run-length based connected component algorithm for FPGA implementation. In: International Conference on Field-Programmable Technology, Taipei, Taiwan. 7-10th Dec