A compact dynamic-performance-improved current-steering DAC with random rotation-based binary-weighted selection

IEEE Journal of Solid-State Circuits

Volumn 47, Issue 2, 2012, Pages 444-453

  Lin, Wei Te ^a   Kuo, Tai Haur ^a  

^a NATIONAL CHENG KUNG UNIVERSITY   (Taiwan)

Author keywords

binary weighted; current steering; DEM; Digital to analog converter; dynamic element matching; Nyquist rate; random rotation based binary weighted selection; SFDR

Indexed keywords

BINARY-WEIGHTED; CURRENT STEERING; DEM; DIGITAL-TO-ANALOG CONVERTERS; DYNAMIC ELEMENT MATCHING; NYQUIST RATE; RANDOM ROTATION-BASED BINARY-WEIGHTED SELECTION; SFDR;

CMOS INTEGRATED CIRCUITS; DESIGN; DIGITAL INTEGRATED CIRCUITS; DIGITAL TO ANALOG CONVERSION;

ROTATION;

EID: 84856497565     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2011.2168651     Document Type: Article

References (23)

1. A. van den Bosch, M. Borremans, M. Steyaert, and W. Sansen, "A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter," IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315-324, Mar. 2001.
2. J. Bastos, A. M. Marques, M. S. J. Steyaert, and W. Sansen, "A 12-bit intrinsic accuracy high-speed CMOS DAC," IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.
3. P. Palmers and M. S. J. Steyaert, "A 10-bit 1.6-GS/s 27-mW current- steering D/A converter with 550-MHz 54-dB SFDR bandwidth in 130-nm CMOS," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 11, pp. 2870-2879, Nov. 2010.
4. C.-H. Lin, F. M. L. van der Goes, J. R. Westra, J. Mulder, Y. Lin, E. Arslan, E. Ayranci, X. Liu, and K. Bult, "A 12 bit 2.9 GS/s DAC with IM3 60>dBc beyond 1 GHz in 65 nm CMOS," IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3285-3293, Dec. 2009.
5. W.-H. Tseng, C.-W. Fan, and J.-T. Wu, "A 12 b 1.25 GS/s DAC in 90 nm CMOS with>70 dB SFDR up to 500 MHz," in IEEE Solid-State Circuits Conf. Dig. Tech. Papers, 2011, pp. 192-193.
6. A. R. Bugeja and B.-S. Song, "A self-trimming 14-b 100-MS/s CMOS DAC," IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841-1852, Dec. 2000.
7. M. P. Tiilikainen, "A 14-bit 1.8-V 20-mW1-mm CMOS DAC," IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1144-1147, Jul. 2001.
8. D.-L. Shen, Y.-C. Lai, and T.-C. Lee, "A 10-bit binary-weighted DAC with digital background LMS calibration," in Proc. IEEE Asian Solid- State Circuits Conf. (ASSCC), Nov. 2007, pp. 352-355.
9. J.-H. Chi, S.-H. Chu, and T.-H. Tsai, "A 1.8-V 12-bit 250 MS/s 25-mW self-calibrated DAC," in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2010, pp. 222-225.
10. D.-H. Lee and T.-H. Kuo, "Randomized thermometer-coding digital- to-analog converter and method therefor," U.S. patent 7,679,539, Mar. 16, 2010.
11. D.-H. Lee, T.-H. Kuo, and K.-L. Wen, "Low-cost 14-bit current- steering DAC with a randomized thermometer-coding method," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 56, no. 2, pp. 137-141, Feb. 2009.
12. D.-H. Lee, Y.-H. Lin, and T.-H. Kuo, "Nyquist-rate current-steering digital-to-analog converters with random multiple data-weighted averaging technique and Q rotated walk switching scheme," IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 11, pp. 1264-1268, Nov. 2006.
13. T. Chen and G. G. E. Gielen, "The analysis and improvement of a current- steering DACs dynamic SFDR-I: The cell-dependent delay difference," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 53, no. 1, pp. 3-15, Jan. 2006.
14. T. Chen and G. G. E. Gielen, "The analysis and improvement of a current-steering DACs dynamic SFDR-II: The output-dependent delay difference," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 54, no. 2, pp. 268-279, Feb. 2007.
15. A. van den Bosch,M. S. J. Steyaert, andW. Sansen, "An accurate yield model for CMOS current-steering D/A converters," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2000, pp. 105-108.
16. Y. Cong and R. L. Geiger, "Switching sequence optimization for gradient error compensation in thermometer-decoded DAC array," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 47, no. 7, pp. 585-595, Jul. 2000.
17. J. Deveugele and M. S. J. Steyaert, "A 10-bit 250-MS/s binary- weighted current-steering DAC," IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 320-329, Feb. 2006.
18. M. Borremans, A. V. den Bosch, M. Steyaert, and W. Sansen, "A low power, 10-bit CMOS D/A converter for high speed applications," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), May 2001, pp. 157-160.
19. Y. Ikeda, M. Frey, and A. Matsuzawa, "A 14-bit 100-MS/s digitally calibrated binary-weighted current-steering CMOS DAC without calibration ADC," in Proc. IEEE Asian Solid-State Circuits Conf. (ASSCC), Nov. 2007, pp. 356-359.
20. A. Van den Bosch, M. S. J. Steyaert, and W. Sansen, "Solving static and dynamic performance limitations for high-speed D/A converters," in Analog Circuit Design: Scalable Analog Circuit Design, High-Speed D/A Converters, RF Power Amplifiers. Norwell, MA: Kluwer, 2002, pp. 189-210.
21. D. Giotta, P. Pessl, M. Clara, W. Klatzer, and R. Gaggl, "Low-power 14-bit current steering DAC for ADSL2+/CO applications in 0.13μm CMOS," in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 163-166.
22. M. Clara, W. Klatzer, B. Seger, A. D. Giandomenico, and L. Gori, "A 1.5 V 200MS/s 13 b 25 mWDAC with randomized nested background calibration in 0.13 mCMOS," in IEEE Solid-State Circuits Conf.Dig. Tech. Papers, 2007, pp. 250-251.
23. T. Chen, P. Geens, G. van der Plas, W. Dehaene, and G. Gielen, "A 14-bit 130-MHz CMOS current-steering DAC with adjustable INL," in Proc. IEEE Eur. Solid-State Circuits Conf. (ESSCIRC), Sep. 2004, pp. 167-170.